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US 8,896,068 B2Granted
Semiconductor device including source/drain regions and a gate electrode, and having contact portions
AssigneeSony Corporation
InventorSatoru Mayuzumi
Life of this patent
Estimating the term…
Abstract
A method for manufacturing a semiconductor device includes the steps of: (a) forming a gate electrode on a substrate, forming source/drain regions and a channel forming region in the substrate, and forming on the source/drain regions a first interlayer insulating layer equal in height to the gate electrode; (b) forming in the first interlayer insulating layer groove-shaped first contact portions connected to the source/drain regions; (c) forming a second interlayer insulating layer on a whole surface; (d) forming hole-shaped second contact portions in portions of the second interlayer insulating layer on the first contact portion; and (e) forming on the second interlayer insulating layer wires connected to the second contact portions.
Claims13
A semiconductor device comprising:
- (A) source and drain regions and a channel forming region in a substrate;
- (B) a gate electrode above the channel forming region with a gate insulating film between the channel forming region and the gate electrode;
- (C) a silicide layer on the substrate over the source and drain regions;
- (D) a stress applying layer on the silicide layer;
- (E) a first interlayer insulating layer on the source and drain regions;
- (F) respective first contact portions in the first interlayer insulating layer and directly connected to the source and drain regions by extending through the stress applying layer and the silicide layer;
- (G) a second interlayer insulating layer on the gate electrode, the first interlayer insulating layer, and the first contact portions;
- (H) respective second contact portions in portions of the second interlayer insulating layer over the first contact portions so that each second contact portion extends to and contacts a respective first contact portion;
- (I) a third contact portion in the second interlayer insulating layer and directly connected to the gate electrode;
- and
- (J) respective wires on the second interlayer insulating layer and connected to the second contact portions and the third contact portion,
- wherein,
- the gate electrode, the first contact portions, and the first interlayer insulating layer have the same height to their top faces,
- each of the first contact portions has a groove shape and has a first dimension that is longer in a first direction than a second dimension in a second direction orthogonal to the first direction,
- in cross section, the source and drain regions are linearly separated in the second direction,
- each of the second contact portions has a hole shape and has substantially equal first and second dimensions in the first and second directions, respectively, and
- the second contact portions and the third contact portion are positioned such that, when viewed in a plan view, the second contact portions and the third contact portion are not aligned along a line that extends in the second direction.
14 more elements
A semiconductor device that comprises an n-channel semiconductor device and a p-channel semiconductor device each of which includes:
- (A) source and drain regions and a channel forming region in a substrate;
- (B) a gate electrode above the channel forming region with a gate insulating film between the gate electrode and the channel forming region;
- (C) a silicide layer on the substrate over the source and drain regions;
- (D) a stress applying layer on the silicide layer;
- (E) a first interlayer insulating layer formed on the source and drain regions;
- (F) respective first contact portions formed in the first interlayer insulating layer and directly connected to the source and drain regions by extending through the stress applying layer and the silicide layer;
- (G) a second interlayer insulating layer formed on the gate electrode, the first interlayer insulating layer, and the first contact portions;
- (H) respective second contact portions formed in portions of the second interlayer insulating layer on the first contact portions;
- and
- (I) respective wires formed on the second interlayer insulating layer and connected to the second contact portions,
- wherein,
- the n-channel and p-channel semiconductor devices are separated by an element isolation region,
- the gate electrode, the first contact portions, and the first interlayer insulating layer have the same height to their top faces,
- each of the first contact portions of the n-channel semiconductor device and each of the first contact portions of the p-channel semiconductor device has a groove shape, each of the first contact portions of each of the n-channel and p-channel semiconductor devices having a first dimension that is longer in a first direction than a second dimension in a second direction orthogonal to the first direction,
- each of the second contact portions of the n-channel semiconductor device and each of the second contact portions of the p-channel semiconductor device has a hole shape, each of the second contact portions of each of the n-channel and p-channel semiconductor devices having substantially equal first and second dimensions in the first and second directions, respectively,
- for each of the n-channel and p-channel semiconductor devices, in cross section, the source and drain regions are linearly separated in the second direction,
- the first contact portions of the n-channel semiconductor device have a tensile stress,
- the first contact portions of the p-channel semiconductor device have a compression stress, and
- the first contact portions of the source and drain regions of the n-channel semiconductor device are respectively joined to the first contact portions of the source and drain regions of the p-channel semiconductor device on the element isolation region.
16 more elements
Dependencies are inferred from the claim text.