Trench power MOSFET

A device comprising:

• a semiconductor region of a first conductivity type selected from the group consisting essentially of p-type and n-type;
• a trench extending from a top surface of the semiconductor region into the semiconductor region;
• a first dielectric layer lining a bottom and sidewalls of the trench;
• a field plate comprising a bottom and sidewalls contacting the first dielectric layer,
• wherein the field plate is conductive;
• a main gate in the trench and overlapping the field plate;
• a second dielectric layer between and separating the main gate and the field plate from each other;
• and
• a Doped Drain (DD) region of the first conductivity type, wherein the DD region comprises a top surface contacting a substantially horizontal bottom surface of the second dielectric layer, and a sidewall contacting the first dielectric layer, wherein the DD region has an impurity concentration greater than an impurity concentration of the semiconductor region, and wherein the main gate comprises a distinguishable vertical interface substantially aligned to an interface between the DD region and the first dielectric layer.

A device comprising:

• a semiconductor region of a first conductivity type;
• a trench extending from a top surface of the semiconductor region into the semiconductor region;
• a first dielectric layer lining a bottom and sidewalls of the trench;
• a field plate comprising a bottom and sidewalls contacting the first dielectric layer, wherein the field plate is conductive;
• a second dielectric layer over and contacting the field plate;
• a Doped Drain (DD) region of the first conductivity type, wherein the DD region comprises a top surface contacting a substantially horizontal bottom surface of the second dielectric layer, and a sidewall contacting the first dielectric layer, wherein the DD region has an impurity concentration greater than an impurity concentration of the semiconductor region;
• and
• a main gate in the trench, wherein an edge portion of the main gate overlaps the DD region, wherein the second dielectric layer is between and separates the main gate and the field plate from each other, and wherein the main gate comprises a distinguishable vertical interface substantially aligned to an interface between the DD region and the first dielectric layer.