Accumulation type FinFET, circuits and fabrication method thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChih Chieh Yeh, Chih-Sheng Chang, Clement Hsingjen Wann
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Abstract
This description relates to a fin field-effect-transistor (FinFET) including a substrate and a fin structure on the substrate. The fin structure includes a channel between a source and a drain, wherein the source, the drain, and the channel have a first type dopant, and the channel comprises at least one of a Ge, SiGe, or III-V semiconductor. The FinFET further includes a gate dielectric layer over the channel and a gate over the gate dielectric layer. The FinFET further includes a nitride spacer on the substrate adjacent the gate and an oxide layer between the nitride spacer and the gate and between the nitride spacer and the substrate.
Claims20
A fin field-effect-transistor (FinFET), comprising:
- a substrate;
- a fin structure on the substrate, the fin structure including a channel between a source and a drain, wherein the source, the drain, and the channel have a first type dopant, and the channel comprises at least one of a Ge, SiGe, or III-V semiconductor;
- a gate dielectric layer over the channel;
- a gate over the gate dielectric layer;
- a nitride spacer on the substrate adjacent the gate;
- and
- an oxide layer between the nitride spacer and the gate and between the nitride spacer and the substrate.
A method for forming a FinFET, comprising:
- forming a fin structure on a substrate, the fin structure including a channel between a source and a drain, wherein the source, the drain, and the channel have a first type dopant, and the channel comprises at least one of a Ge, SiGe, or III-V semiconductor;
- forming a gate dielectric layer over the channel;
- forming a gate over the gate dielectric layer
- forming a nitride spacer on the substrate adjacent the gate;
- and
- forming an oxide layer between the nitride spacer and the gate and between the nitride spacer and the substrate.
An integrated circuit, comprising:
- a substrate;
- a dummy pattern including at least one of a first fin structure on the substrate, the first fin structure comprising a first channel between a first source and a first drain, wherein the first source, the first drain, and the first channel have a first type dopant;
- and
- a FinFET over the substrate, the FinFET including:
- a second fin structure on the substrate, the second fin structure including a channel between a source and a drain, wherein the source, the drain, and the channel have a first type dopant, and the channel comprises at least one of a Ge, SiGe, or III-V semiconductor;
- a gate dielectric layer over the channel;
- a gate over the gate dielectric layer;
- a nitride spacer on the substrate adjacent the gate;
- and
- an oxide layer between the nitride spacer and the gate and between the nitride spacer and the substrate.
Dependencies are inferred from the claim text.