Semiconductor device
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorKiyoshi Kato
Life of this patent
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Abstract
Provided is a semiconductor device with a novel structure in which stored data can be retained even when power is not supplied, and which does not have a limitation on the number of writing. The semiconductor device includes both a memory circuit including a transistor including an oxide semiconductor (in a broader sense, a transistor whose off-state current is sufficiently small), and a peripheral circuit such as a driver circuit including a transistor including a material other than an oxide semiconductor (that is, a transistor capable of operating at sufficiently high speed). Further, the peripheral circuit is provided in a lower portion and the memory circuit is provided in an upper portion, so that the area and size of the semiconductor device can be decreased.
Claims14
A semiconductor device comprising:
- a peripheral circuit formed by utilizing a semiconductor substrate;
- a memory cell array over the peripheral circuit;
- and
- an insulating layer between the peripheral circuit and the memory cell array, the insulating layer comprising an opening,
- wherein the peripheral circuit comprises a plurality of sense latches arranged in matrix,
- wherein the memory cell array comprises a plurality of memory cells arranged in matrix,
- wherein each of the plurality of memory cells comprises:
- a transistor comprising a gate electrode, a source electrode, a drain electrode, a gate insulating layer, and an oxide semiconductor layer;
- and
- a capacitor,
- wherein each of the plurality of sense latches comprises a first terminal and a second terminal, and
- wherein at least one of the first terminal and the second terminal is electrically connected via at least an electrode in the opening of the insulating layer to one of the source electrode and the drain electrode of the transistor.
A semiconductor device comprising:
- a peripheral circuit formed by utilizing a semiconductor substrate;
- a plurality of memory cell arrays stacked over the peripheral circuit;
- and
- an insulating layer between the peripheral circuit and the plurality of memory cell arrays, the insulating layer comprising an opening,
- wherein the peripheral circuit comprises a plurality of sense latches arranged in matrix,
- wherein each of the plurality of memory cell arrays comprises a plurality of memory cells arranged in matrix,
- wherein each of the plurality of memory cells comprises:
- a transistor comprising a gate electrode, a source electrode, a drain electrode, a gate insulating layer, and an oxide semiconductor layer;
- and
- a capacitor,
- wherein each of the plurality of sense latches comprises a first terminal and a second terminal, and
- wherein at least one of the first terminal and the second terminal is electrically connected via at least an electrode in the opening of the insulating layer to one of the source electrode and the drain electrode of the transistor.
A semiconductor device comprising:
- a peripheral circuit formed by utilizing a semiconductor substrate;
- a first memory cell array and a second memory cell array stacked over the peripheral circuit;
- and
- an insulating layer between the peripheral circuit and the first memory cell array, the insulating layer comprising an opening,
- wherein the peripheral circuit comprises a plurality of sense latches arranged in matrix,
- wherein each of the first memory cell array and the second memory cell array comprises a plurality of memory cells arranged in matrix,
- wherein each of the plurality of memory cells included in the first memory cell array comprises:
- a first transistor comprising a first gate electrode, a first source electrode, a first drain electrode, a first gate insulating layer, and a first oxide semiconductor layer;
- and
- a first capacitor,
- wherein each of the plurality of memory cells included in the second memory cell array comprises:
- a second transistor comprising a second gate electrode, a second source electrode, a second drain electrode, a second gate insulating layer, and a second oxide semiconductor layer;
- and
- a second capacitor,
- wherein each of the plurality of sense latches comprises a first terminal and a second terminal, and
- wherein at least one of the first terminal and the second terminal is electrically connected via at least an electrode in the opening of the insulating layer to one of the first source electrode and the first drain electrode of the first transistor, and one of the second source electrode and the second drain electrode of the second transistor.
Dependencies are inferred from the claim text.