Integrated circuits with selective gate electrode recess

An integrated circuit device, comprising:

• a first MOS transistor disposed over a first portion of a substrate wherein the first MOS transistor comprises:
• a first semiconductor channel region;
• and
• a first gate electrode having a first bottom electrode surface proximate to a first gate dielectric disposed over the first semiconductor channel region and having a first top electrode surface at a first height from the first bottom gate electrode surface;
• and
• a second MOS transistor disposed over a second portion of the substrate, wherein the second MOS transistor comprises:
• a second semiconductor channel region;
• and
• a second gate electrode having a second bottom electrode surface proximate to a second gate dielectric disposed over the second semiconductor channel region and having at least a portion of a second top electrode surface at a second height from the second bottom electrode surface that is different than the first height, wherein the first and second gate electrodes further comprise at least a bulk material and a work function material, the work function material disposed between the bulk material and the gate dielectric and also along opposite sidewalls of the bulk material with both the bulk material and the work function material present at portions of the first and second top electrode surfaces, and wherein at least the bulk material of the first gate electrode is recessed relative to at least a portion of the second top electrode surface.

An integrated circuit device, comprising:

• a first MOS transistor disposed over a first portion of a substrate, wherein the first MOS transistor comprises:
• a first semiconductor channel region;
• and
• a first gate electrode having a first bottom electrode surface proximate to a first gate dielectric disposed over the first semiconductor channel region and having a first top electrode surface at a first height from the first bottom gate electrode surface;
• and
• a second MOS transistor disposed over a second portion of the substrate, wherein the second MOS transistor comprises:
• a second semiconductor channel region;
• and
• a second gate electrode having a second bottom electrode surface proximate to a second gate dielectric disposed over the second semiconductor channel region and having at least a portion of a second top electrode surface at a second height from the second bottom electrode surface that is smaller than the first height, wherein the second gate dielectric has a top dielectric surface at a third height from the second bottom gate electrode surface that is larger than the second height.

An integrated circuit device, comprising:

• a first MOS transistor disposed over a first portion of a substance, wherein the first MOS transistor comprises:
• a first semiconductor channel region;
• and
• a first gate electrode having a first bottom electrode surface proximate to a first gate dielectric disposed over the first semiconductor channel region and having a first top electrode surface at a first height from the first bottom gate electrode surface;
• a second MOS transistor disposed over a second portion of the substrate, wherein the second MOS transistor comprises:
• a second semiconductor channel region;
• and
• a second gate electrode having a second bottom electrode surface proximate to a second gate dielectric disposed over the second semiconductor channel region and having at least a portion of a second top electrode surface at a second height from the second bottom electrode surface that is different than the first height;
• a first semiconductor source and drain on opposite sides of the first semiconductor channel region;
• a first spacer dielectric disposed between the first gate electrode and the first semiconductor source and drain;
• a second semiconductor source and drain on opposite sides of the second semiconductor channel region;
• and
• a second spacer dielectric disposed between the second gate electrode and the second semiconductor source and drain, wherein the first top electrode surface is recessed below a top surface portion of the first spacer dielectric by an amount greater than is the second top electrode surface relative to the second spacer dielectric.