Array substrate for fringe field switching mode liquid crystal display device and method of fabricating the same

A method of manufacturing an array substrate for a fringe field switching mode liquid crystal display device, comprising:

• forming a gate line, a gate pad electrode and a common line on a substrate including a display area and a non-display area, the gate line and the common line spaced apart from each other and extending along a first direction in the display area, the gate pad electrode connected to the gate line and disposing in the non-display area;
• forming a gate insulating layer on the gate line, the gate pad electrode and the common line;
• forming a data line and a data pad electrode on the gate insulating layer, the data line extending along a second direction in the display area and crossing the gate line to define a pixel region, the data pad electrode connected to the data line and disposing in the non-display area;
• forming a thin film transistor electrically connected to the gate and data lines;
• forming a first passivation layer over the thin film transistor, the data line and the data pad electrode;
• forming a second passivation layer on the first passivation layer and having a flat top surface, the second passivation layer including a common contact hole exposing the common line and first, second and third contact holes exposing a drain electrode of the thin film transistor, the gate pad electrode and the data pad electrode, respectively, the second passivation layer having a first thickness in the display area and a second thickness in the non-display area, the second thickness being smaller than the first thickness;
• forming a common electrode on the second passivation layer, the common electrode having a first opening corresponding to the thin film transistor and connected to the common line through the common contact hole;
• forming a third passivation layer on the common electrode, the third passivation layer including a drain contact hole exposing the drain electrode, a gate pad contact hole exposing the gate pad electrode and a data pad contact hole exposing the data pad electrode corresponding to the first, second and third contact holes, respectively;
• and
• forming a pixel electrode, a gate auxiliary pad electrode and a data auxiliary pad electrode on the third passivation layer, the pixel electrode connected to the drain electrode through the drain contact hole and including second openings of a bar shape in the pixel region, the gate auxiliary pad electrode connected to the gate pad electrode through the gate pad contact hole, the data auxiliary pad electrode connected to the data pad electrode through the data pad contact hole.