Implementing enhanced power supply distribution and decoupling utilizing TSV exclusion zone

A structure for implementing enhanced power supply distribution and decoupling utilizing Through-Silicon-Via (TSV) exclusion zone areas on a semiconductor chip comprising:

• a substrate;
• a plurality of metal layers disposed on said substrate;
• a dielectric layer disposed between adjacent ones of said plurality of said metal layers;
• at least one of said plurality of said metal layers having a first wiring shape having a hole of a first diameter;
• a second hole in a dielectric above the first wiring level having a second diameter, the second hole being concentric with the first hole, and the second diameter being larger than the first diameter;
• a conductive via fill extending through said substrate, said plurality of metal layers, and said dielectric layer disposed between adjacent ones of said plurality of said metal layers;
• said conductive via fill having approximately said first diameter below said dielectric and said conductive via fill having approximately said second diameter proximate said dielectric layer making electrical connection to said first wiring shape;
• said conductive via fill electrically connected to a selected one of voltage supply rail VDD and voltage supply rail ground GND potential;
• and
• wire loops selectively encircling said conductive via fill and connected to a selected one of voltage supply rail VDD and voltage supply rail ground GND potential based upon power attributes of said conductive via fill.