Back to results
US 8,895,426 B2Granted
Metal gate transistor, integrated circuits, systems, and fabrication methods thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorJeff J. Xu
Life of this patent
Estimating the term…
Abstract
A gate-last method for forming a metal gate transistor is provided. The method includes forming an opening within a dielectric material over a substrate. A gate dielectric structure is formed within the opening and over the substrate. A work function metallic layer is formed within the opening and over the gate dielectric structure. A silicide structure is formed over the work function metallic layer.
Claims20
A gate-last method for forming a metal gate transistor, the method comprising:
- forming a work function metallic layer within an opening and over a gate dielectric structure;
- and
- forming a silicide structure over the work function metallic layer,
- wherein the forming the silicide structure comprises:
- forming a silicon bulk within the opening;
- removing a portion of the silicon bulk to form a recess within the opening;
- and
- saliciding the silicon bulk with a metallic material to form the silicide structure.
5 more elements
A method for forming a transistor comprising:
- forming a dummy gate over a gate dielectric structure, the dummy gate and the gate dielectric structure being surrounded by a dielectric layer over a substrate;
- removing the dummy gate;
- forming a work function metallic layer over the gate dielectric structure;
- forming a silicon bulk over the work function metallic layer, a top surface of the silicon bulk being lower than a top surface of the dielectric layer;
- and
- saliciding the silicon bulk with a metallic material to form a silicide structure.
3 more elements
A method for forming a gate structure comprising:
- forming a gate dielectric structure, the gate dielectric structure being surrounded by a dielectric layer over a substrate;
- forming a silicon bulk over the gate dielectric structure;
- forming a layer of a metallic material over a top surface of the silicon bulk and a top surface of the dielectric layer, wherein the top surface of the silicon bulk is lower than the top surface of the dielectric layer;
- and
- saliciding the silicon bulk with the metallic material to form a silicide structure.
2 more elements
Dependencies are inferred from the claim text.