Monolithic integration of photonics and electronics in CMOS processes

#[Not Applicable]

#[Not Applicable]

#Certain embodiments of the invention relate to semiconductor processing. More specifically, certain embodiments of the invention relate to a method and system for monolithic integration of photonics and electronics in CMOS processes.

#FIG. 1A is a block diagram of a photonically enabled CMOS chip, in accordance with an embodiment of the invention.

#FIG. 1B is a diagram illustrating an oblique view of an exemplary photonically enabled CMOS chip, in accordance with an embodiment of the invention.

#FIG. 1C is a diagram illustrating an exemplary CMOS chip coupled to an optical fiber cable, in accordance with an embodiment of the invention.

#Certain aspects of the invention may be found in a method and system for monolithic integration of photonics and electronics in CMOS processes. Exemplary aspects of the invention may comprise fabricating photonic and electronic devices on a single complementary metal-oxide semiconductor (CMOS) wafer with different silicon layer thicknesses for the photonic and the electronic devices. The electronic and photonic devices may be fabricated on a semiconductor-on-insulator (SOI) wafer utilizing a bulk CMOS process. The electronic and photonic devices may be fabricated on a SOI wafer utilizing a SOI CMOS process. The different silicon layer thicknesses may be fabricated utilizing a double SOI process and/or a selective area growth process. Cladding layers for the photonic devices may be fabricated utilizing one or more oxygen implants into the CMOS wafer and/or utilizing CMOS trench oxide on the CMOS wafer. Silicon material for the photonic devices may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers for the photonic devices may be fabricated utilizing selective backside etching regions of the CMOS wafer below the photonic devices. Reflective surfaces for the photonic devices may be fabricated by depositing metal on the selectively etched regions of the CMOS wafer. Silicon dioxide integrated in the CMOS wafer using oxygen implant may be utilized as an etch stop layer for the backside etching. Silicon germanium integrated in the CMOS wafer may be utilized as an etch stop layer for the backside etching. Photonic and electronic devices may be fabricated on two complementary metal-oxide semiconductor (CMOS) wafers with different silicon layer thicknesses for the photonic and the electronic devices by bonding at least a portion of each of the wafers together, where one of the CMOS wafers comprises the photonic devices and the other CMOS wafer comprises the electronic devices.

#FIG. 1A is a block diagram of a photonically enabled CMOS chip, in accordance with an embodiment of the invention. Referring to FIG. 1A, there is shown optoelectronic devices on a CMOS chip 130 comprising high speed optical modulators 105A-105D, high-speed photodiodes 111A-111D, monitor photodiodes 113A-113H, and optical devices comprising taps 103A-103K, optical terminations 115A-115D, and grating couplers 117A-117H. There is also shown electrical devices and circuits comprising transimpedance and limiting amplifiers (TIA/LAs) 107A-107E, analog and digital control circuits 109, and control sections 112A-112D. Optical signals are communicated between optical and optoelectronic devices via optical waveguides fabricated in the CMOS chip 130. Additionally, optical waveguides are indicated in FIG. 1A by the dashed ovals.

#The high speed optical modulators 105A-105D comprise Mach-Zehnder or ring modulators, for example, and enable the modulation of the CW laser input signal. The high speed optical modulators 105A-105D are controlled by the control sections 112A-112D, and the outputs of the modulators are optically coupled via waveguides to the grating couplers 117E-117H. The taps 103D-103K comprise four-port optical couplers, for example, and are utilized to sample the optical signals generated by the high speed optical modulators 105A-105D, with the sampled signals being measured by the monitor photodiodes 113A-113H. The unused branches of the taps 103D-103K are terminated by optical terminations 115A-115D to avoid back reflections of unwanted signals.