Methods of fabricating semiconductor devices having buried word line interconnects

A method of fabricating a semiconductor device, comprising:

• providing a semiconductor substrate having a cell region and a peripheral circuit region;
• forming an isolation layer defining cell active regions in the cell region and peripheral circuit active regions in the peripheral circuit region;
• etching the cell active regions and the isolation layer, and simultaneously forming word line trenches in the cell region and interconnect trenches in the peripheral circuit region;
• simultaneously forming word line patterns extending longitudinally along a first direction in the word line trenches and interconnect patterns extending longitudinally beyond ends of the word line patterns along the first direction in the interconnect trenches;
• forming gate lines on the semiconductor substrate having the interconnect patterns, the gate lines having regions overlapping the interconnect patterns;
• etching-back the word line patterns and the interconnect patterns to form word lines and interconnects, the interconnects having first portions at a same level as the word lines and second portions that extend vertically from the first portions to contact bottom surfaces of the gate lines overlying the first portions of the interconnects;
• and
• forming an insulating pattern on the word lines and the buried interconnects.

A method of fabricating a semiconductor device, comprising:

• providing a semiconductor substrate having a cell region and a peripheral circuit region;
• forming an isolation layer defining cell active regions in the cell region and peripheral circuit active regions in the peripheral circuit region;
• etching the cell active regions and the isolation layer, and simultaneously forming word line trenches in the cell region and interconnect trenches in the peripheral circuit region;
• simultaneously forming buried word lines in the word line trenches and buried interconnects in the interconnect trenches, the buried interconnects in contact with ends of respective ones of the buried word lines and extending longitudinally beyond ends thereof;
• forming gate lines on the semiconductor substrate having the buried interconnects, the gate lines having regions overlapping the buried interconnects, the buried interconnects contacting bottom surfaces of the overlapping regions;
• and
• forming an insulating pattern on the buried word lines and the buried interconnects disposed at a lower level than top surfaces of the adjacent active regions.