Memory devices including vertical pillars and methods of manufacturing and operating the same

A method of fabricating a semiconductor device comprising:

• providing a substrate having a first dopant type;
• vertically stacking a plurality of gate patterns on the substrate;
• forming a vertical channel penetrating the plurality of gate patterns to be connected with the substrate, the vertical channel having the first dopant type;
• forming a data storage layer between the gate patterns and the vertical channel;
• and
• forming a source region in the substrate to be spaced apart from the vertical channel,
• wherein the source region has a second dopant type different from the first dopant type.

A method of fabricating a semiconductor device, comprising:

• providing a semiconductor substrate extending in a horizontal direction;
• providing a plurality of gate patterns and a plurality of insulating patterns alternately and vertically stacked on the substrate;
• providing a first vertical channel of semiconductor material penetrating the gate patterns and the insulating patterns;
• providing a gate insulating layer disposed between the plurality of gate patterns and the first vertical channel;
• and
• providing a horizontal channel connected to an end of the first vertical channel.

A method of fabricating a semiconductor device, comprising:

• providing a semiconductor substrate extending in a horizontal direction;
• providing a horizontal channel formed of semiconductor material extending in the horizontal direction;
• providing a plurality of NAND cell strings, each of the plurality of NAND cell strings comprising a semiconductor pillar extending in a vertical direction connected to the horizontal channel;
• providing a vertical stack of a plurality of gate patterns and a plurality of insulating patterns alternately stacked on the substrate, each semiconductor pillars extending through the vertical stack of gate patterns and insulating patterns,
• wherein a lowermost gate pattern of the plurality of gate patterns is positioned adjacent the horizontal channel to activate the horizontal channel.

A method of fabricating a semiconductor device, the method comprising:

• providing a semiconductor substrate extending in a horizontal direction;
• providing a lowermost gate pattern on the semiconductor substrate;
• providing a plurality of gate patterns and a plurality of insulating patterns alternately and vertically stacked on the lowermost gate pattern, the lowermost gate pattern being nearer to the surface of the semiconductor substrate than the plurality of gate patterns;
• providing a first vertical channel penetrating the gate patterns and the insulating patterns;
• providing a gate insulating layer disposed between the plurality of gate patterns and the first vertical channel;
• and
• providing a horizontal channel connected to an end of the first vertical channel.

A method of fabricating a three-dimensional non-volatile memory device, the method comprising:

• providing a first select gate on a semiconductor substrate;
• providing a second select gate on the semiconductor substrate;
• providing a vertical channel extending in a vertical direction on the substrate;
• and
• providing a plurality of memory cells between the first select gate and the second select gate, the plurality of memory cells coupled in series by the vertical channel,
• wherein the first select gate is configured to generate a horizontal channel when receiving a voltage.