Method of forming semiconductor structure

A method of forming a semiconductor structure, comprising:

• providing a substrate, the substrate having a cell area, a logic circuit area, and a resistor area;
• sequentially forming an oxide material layer and a first conductive material layer on the substrate;
• performing a patterning step to form a first stacked structure on the substrate in the cell area, and form a second stacked structure on the substrate in the logic circuit area, and form a third stacked structure on the substrate in the resistor area;
• forming a first spacer on a sidewall of the first stacked structure, forming a second spacer on a sidewall of the second stacked structure, and forming a third spacer on a sidewall of the third stacked structure;
• forming two first doped regions in the substrate beside the first stacked structure, and forming two second doped regions in the substrate beside the second stacked structure;
• and
• forming a dielectric layer and a second conductive layer on the first stacked structure, wherein the dielectric layer and the second conductive layer are further formed on the third stacked structure in a manner such that the dielectric layer and the second conductive layer do not cover a portion of an upper surface of the third stacked structure,
• wherein the first stacked structure, the patterned dielectric layer, and the patterned second conductive layer in the cell area constitute a charge storage structure, and the second stacked structure is a logic transistor.

A method of forming a semiconductor structure, comprising:

• providing a substrate, the substrate having a cell area, a logic circuit area, and a resistor area;
• sequentially forming an oxide material layer and a first conductive material layer on the substrate;
• performing a patterning step to form a first stacked structure on the substrate in the cell area, and form a second stacked structure on the substrate in the logic circuit area;
• forming a first spacer on a sidewall of the first stacked structure, and forming a second spacer on a sidewall of the second stacked structure;
• forming two first doped regions in the substrate beside the first stacked structure, and forming two second doped regions in the substrate beside the second stacked structure;
• and
• forming a dielectric layer and a second conductive layer on the first stacked structure, wherein the dielectric layer and the second conductive layer are further formed on the substrate in the resistor area to constitute a third stacked structure,
• wherein the first stacked structure, the dielectric layer, and the second conductive layer in the cell area constitute a charge storage structure, and the second stacked structure is a logic transistor.

A method of forming a semiconductor structure, comprising:

• providing a substrate, the substrate having a cell area, a logic circuit area, and a capacitor area;
• sequentially forming an oxide material layer and a first conductive material layer on the substrate;
• performing a patterning step to form a first stacked structure on the substrate in the cell area, form a second stacked structure on the substrate in the logic circuit area, and form a third stacked structure on the substrate in the capacitor area;
• forming a first spacer on a sidewall of the first stacked structure, forming a second spacer on a sidewall of the second stacked structure, and forming a third spacer on a sidewall of the third stacked structure;
• forming two first doped regions in the substrate beside the first stacked structure, and forming two second doped regions in the substrate beside the second stacked structure;
• forming a dielectric material layer and a second conductive material layer on the substrate covering the first, second and third stacked structures and covering the first, second and third spacers;
• and
• patterning the dielectric material layer and the second conductive material layer, so as to form a first dielectric layer and a first gate layer on the first stacked structure and form a second dielectric layer and a second gate layer on the third stacked structure,
• wherein the first stacked structure, the first dielectric layer, and the first gate conductive layer in the cell area constitute a charge storage structure, and the second stacked structure is a logic transistor, and the third stacked structure, the second dielectric layer, and the second gate layer in the capacitor area constitute a capacitor.