Fabrication method of semiconductor package

#The present invention relates to semiconductor packages and fabrication methods thereof, and more particularly, to a flip-chip semiconductor package and a fabrication method thereof.

#A molded flip-chip semiconductor package is comprised of a semiconductor chip electrically connected to a surface of a substrate via a plurality of solder bumps mounted on an active surface of the semiconductor chip, an encapsulant formed on the surface of the substrate by a molding process to encapsulate the semiconductor chip, and a plurality of solder balls implanted on an opposite surface of the substrate and serving as I/O terminals for electrically connecting the semiconductor chip to an external device. Such package design greatly reduces the size of the package, such that the semiconductor chip and the substrate can be made comparable in size. The flip-chip design also eliminates the use of conventional bonding wires, thereby desirably reducing impedance and enhancing electrical performance of the package. Accordingly, the flip-chip package represents a mainstream packaging technology nowadays. The related prior arts include U.S. Pat. Nos. 6,038,136, 6,867,487, and Taiwanese Patent No. 1244145.

#With a semiconductor chip becoming larger (greater than 15 mm×15 mm), due to mismatch in coefficient of thermal expansion (CTE) between the semiconductor chip and the encapsulant and also a large contact area therebetween, both the thermal stress and thermal deformation arising during the thermal cycle of chip packaging are directly proportional to a corner-to-center distance of the semiconductor chip, that is, δ (deformation)=α (coefficient of thermal expansion)×L (a distance from a location where deformation=0)×Δt (amount of temperature variation). In particular, corners of a flip-chip semiconductor chip 10 (as shown in FIG. 1) are located farthest from the center of the chip 10 (where deformation=0) and thereby are subjected to the greatest thermal stress and thermal deformation. As a result, delamination usually occurs at the corners of the semiconductor chip and adversely affects the product quality.

#The present invention can be more fully understood by reading the following detailed description of the preferred embodiments, with reference made to the accompanying drawings, wherein:

#FIG. 1 (PRIOR ART) is a cross-sectional view of a conventional flip-chip semiconductor package;

#FIGS. 2A to 2C are schematic diagrams showing a semiconductor package and a fabrication method thereof in accordance with the present invention; and

#Preferred embodiments of a semiconductor packages and a fabrication method thereof as proposed in the present invention are described as follows with reference to FIGS. 2 to 5. It should be understood that the drawings are simplified schematic diagrams only showing the elements relevant to the present invention, and the layout of elements could be more complicated in practical implementation.

#FIGS. 2A to 2C show a semiconductor package and a fabrication method thereof in accordance with the present invention.

#As shown in FIGS. 2A and 2B, wherein FIG. 2B is a cross-sectional view of FIG. 2A taken along line 2B-2B, a semiconductor package of the present invention comprises a semiconductor chip 20. The semiconductor chip 20 has an active surface 201 and a non-active surface 202 opposing to the active surface 201. A roughened structure 200 is formed on a peripheral portion of the non-active surface 202 of the semiconductor chip 20, such that the non-active surface 202 is divided into a non-roughened central portion, and the peripheral portion formed with the roughened structure 200.