Method to improve nucleation of materials on graphene and carbon nanotubes

A method of fabricating a field-effect transistor (FET) device comprising the steps of:

• providing a substrate;
• forming a carbon-based material on the substrate, wherein the carbon-based material comprises graphene;
• forming source and drain region electrodes on a surface of the carbon-based material using electron beam lithography with a poly(methyl methacrylate (PMMA) resist process and contact metal evaporation, wherein the source and drain region electrodes are spaced apart from one another so as to permit a gate electrode to be formed therebetween;
• depositing an ultra thin silicon nucleation layer to a thickness of from about two angstroms to about 10 angstroms on at least a portion of an exposed area of the surface of the carbon-based material to facilitate nucleation of a dielectric layer on the surface of the carbon-based material yet leaving electrical characteristics of the carbon-based material unaffected by the ultra thin silicon nucleation layer, wherein the ultra thin silicon nucleation layer is present only on the surface of the carbon-based material, and comprises amorphous silicon;
• creating a neutral charge state in the ultra thin silicon nucleation layer;
• depositing the dielectric layer over the ultra thin silicon nucleation layer as a continuous layer on the surface of the carbon-based material and covering at least a portion of the source and drain region electrodes having a thickness of from about two angstroms to about 100 angstroms, wherein the neutral charge state is created in the ultra thin silicon nucleation layer by depositing the dielectric layer over the ultra thin silicon nucleation layer in situ, wherein the ultra thin silicon nucleation layer, as deposited, forms a non-continuous layer directly on the exposed area of the surface of the carbon-based material and wherein the non-continuous layer facilitates nucleation of the dielectric that is continuous on the surface of the carbon-based material;
• removing portions of the dielectric layer to expose the source and drain region electrodes;
• and
• after the source and drain region electrodes have been exposed, forming the gate electrode over the dielectric layer between the source and drain region electrodes.