Methods for improving double patterning route efficiency
AssigneeGlobalfoundries Inc.
InventorsYunfei Deng, Lei Yuan, Hidekazu Yoshida, Juhan Kim, Mahbub Rashed, Jongwook Kye
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Abstract
A design methodology for routing for an integrated circuit is disclosed. The method includes placement of cells having double diffusion breaks, which create an extended intercell region. Metal layer prohibit zones are defined to prohibit any M1 structures in the prohibit zones. Metal layer allow zones are placed adjacent to outer metal lines, and jogs are formed in the metal layer allow zones. Vias and viabars may then be applied on the jogs.
Claims20
A method for designing an integrated circuit, comprising:
- arranging a plurality of cells, wherein each cell of the plurality of cells includes a plurality of metal lines which comprise inner metal lines and outer metal lines, and an intercell region disposed between each cell of the plurality of cells;
- identifying a metal layer prohibit zone for each of the plurality of cells;
- identifying a metal layer allow zone adjacent to the outer metal lines for each of the plurality of cells;
- identifying metal layer lines that are candidates to have a jog applied to them;
- applying a jog to the identified metal layer lines;
- and
- applying a via on the jog.
A system for designing an integrated circuit, comprising one or more processors coupled to non-transitory memory containing machine instructions, that when executed by the one or more processors, perform the functions of:
- arranging a plurality of cells including a plurality of metal lines which comprise inner metal lines and outer metal lines, and an intercell region disposed between each cell of the plurality of cells;
- establishing a metal layer prohibit zone for each of the plurality of cells;
- establishing a metal layer allow zone adjacent to the outer metal lines for each of the plurality of cells;
- identifying metal layer lines that are candidates to have a jog applied to them;
- and
- applying a jog to the identified metal layer lines.
An integrated circuit comprising:
- a plurality of cells, wherein each cell of the plurality of cells includes a plurality of metal lines which comprise inner metal lines and outer metal lines, and an intercell region disposed between each cell of the plurality of cells;
- and
- a metal layer line within at least one cell of the plurality of cells, disposed adjacent to an intercell region, wherein the metal layer line comprises a jog.
Dependencies are inferred from the claim text.