Multirate transmission system and method for parallel input data

An apparatus for sending parallel input data comprising:

• a buffer configured to store said parallel input data based on a received parallel data clock that can range from a minimum to a maximum value;
• a control module configured to control, based on a serializer reference clock having a clock frequency that is higher than the maximum clock frequency of the parallel data clock:
• reading said parallel input data from the buffer at a rate that prevents overflow and underflow of said buffer, and
• generating information related to said parallel data clock and generating control characters when parallel input data is not read from the buffer;
• a multiplexer configured to store the read parallel input data, the information related to said parallel data clock and said control characters;
• and
• a serializer, in cooperative engagement with said multiplexer, configured to convert the read parallel input data, the information related to said parallel data clock and the control characters into a serial data stream for transmission.

An apparatus for receiving serial data comprising:

• a deserializer having a clock frequency controlled by a serializer reference clock, configured to receive said serial data containing parallel input data, information related to a parallel data clock of the parallel input data having a clock frequency that can range from a maximum clock frequency to a minimum clock frequency, and control characters, and configured to convert the received serial data into said parallel input data, information related to said parallel data clock, and control characters, wherein the serializer reference clock has a clock frequency that is higher than the maximum clock frequency of the parallel input data;
• a demultiplexer configured to receive the parallel input data and information related to said parallel data clock from the deserializer;
• a buffer configured to store the parallel input data from the demultiplexer;
• and
• a control module configured to receive control characters from the deserializer and the information related to said parallel data clock, configured to control the transfer of parallel input data to the demultiplexer, configured to control the writing of parallel input data to the buffer, and configured to control the determination of at least an approximation of said parallel data clock based on the information related to said parallel data clock so that the parallel input data read from the buffer is received at the determined parallel data clock corresponding to the parallel data clock of the parallel input data.

An apparatus for sending and receiving parallel input data comprising:

• a transmitter portion having:
• a first buffer configured to restore said parallel input data based on a received parallel data clock that can range from a minimum to a maximum value;
• a control module configured to control, based on a serializer reference clock having a clock frequency that is higher than the maximum clock frequency of the parallel data clock:
• reading of said parallel data from the buffer at a rate that prevents overflow and underflow of said buffer, and
• generating information related to said parallel data clock and generating control characters when data is not read from the first buffer;
• a multiplexer configured to store the information related to said parallel data clock and said control characters;
• a serializer in cooperative engagement with said multiplexer, configured to convert the parallel data, the information related to said parallel data clock, and the control characters into serial data for transmission;
• and
• a serial data transmitter configured to transmit said serial data;
• and
• a receiver portion having:
• a deserializer having a clock frequency controlled by a serializer reference clock configured to receive said serial data and configured to convert the received serial data into said parallel input data, information related to said parallel data clock, and control characters, wherein the serializer reference clock has a clock frequency that is higher than the maximum clock frequency of the parallel input data into parallel data, control characters and information related to said parallel data clock;
• a demultiplexer configured to receive the parallel input data and information related to said parallel data clock from the deserializer;
• a second buffer configured to store the parallel input data from the demultiplexer;
• and
• a control module configured to receive the control characters from the deserializer and the information related to said parallel data clock, configured to control the transfer of parallel input data to the demultiplexer, configured to control the writing of parallel input data to the second buffer, and configured to control the determination of at least an approximation of said parallel data clock based on said information related to said parallel data clock so that the parallel input data read from the second buffer is read at the determined parallel data clock corresponding to the parallel data clock of the parallel input data.