Methods of forming printable integrated circuit devices by selective etching to suspend the devices from a handling substrate and devices formed thereby

A method of forming an integrated circuit device, comprising:

• forming a substrate comprising a semiconductor active layer on an underlying sacrificial layer;
• forming a multi-layer electrical interconnect network comprising a plurality of interlayer dielectric layers, on the substrate;
• selectively etching through the plurality of interlayer dielectric layers to expose an upper surface of the semiconductor active layer;
• encapsulating the multi-layer electrical interconnect network with an inorganic capping layer that contacts the exposed upper surface of the semiconductor active layer, wherein said encapsulating comprises depositing an amorphous silicon capping layer at a temperature of less than about 350° C. using a plasma-enhanced deposition technique;
• selectively etching through the inorganic capping layer and the semiconductor active layer to expose the sacrificial layer;
• and then
• removing the sacrificial layer from the substrate to thereby suspend the semiconductor active layer from the substrate.

A method of forming an integrated circuit device, comprising:

• forming a sacrificial layer on a handling substrate;
• forming a semiconductor active layer on the sacrificial layer;
• selectively etching through semiconductor active layer and the sacrificial layer in sequence to define a trench therein having a bottom adjacent the handling substrate;
• filling the trench within an inorganic anchor;
• selectively etching through the semiconductor active layer to thereby expose the sacrificial layer;
• and
• removing the sacrificial layer from between the handling substrate and the semiconductor active layer to thereby suspend the semiconductor active layer from the inorganic anchor,
• wherein said selectively etching through the semiconductor active layer to thereby expose the sacrificial layer is preceded by encapsulating the multi-layer electrical interconnect network with an inorganic capping layer.

A method of forming an integrated circuit device, comprising:

• selectively etching through a multi-layer electrical interconnect network to expose a semiconductor active layer;
• encapsulating the multi-layer electrical interconnect network with an inorganic capping layer that contacts the semiconductor active layer;
• selectively etching through the inorganic capping layer and the semiconductor active layer in sequence to expose a sacrificial layer extending between the semiconductor active layer and a handling substrate;
• and
• removing the sacrificial layer to thereby suspend the semiconductor active layer and the encapsulated multi-layer electrical interconnect network opposite the handling substrate.