Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices

A method of packaging a semiconductor device, the method comprising:

• forming a plurality of through-package vias (TPVs) over a carrier;
• coupling a plurality of integrated circuit dies to the carrier, each of the plurality of integrated circuit dies including a plurality of contact pads, a passivation layer disposed over a portion of the plurality of contact pads, and a polymer layer disposed over the passivation layer;
• forming a molding material over the carrier, the plurality of TPVs, and the plurality of integrated circuit dies;
• removing the molding material from over a top surface of the polymer layer of the plurality of integrated circuit dies;
• forming an opening in the polymer layer of the plurality of integrated circuit dies over each of the plurality of contact pads using a laser drilling process;
• forming a redistribution layer (RDL) over the top surface of the polymer layer and the plurality of openings in the polymer layer, a portion of the RDL being coupled to a top surface of each of the plurality of contact pads;
• removing the carrier;
• and
• singulating the plurality of integrated circuit dies to form a plurality of packaged semiconductor devices.

A packaged semiconductor device, comprising:

• an integrated circuit die including a first side and a second side opposite the first side;
• a plurality of contact pads disposed on the first side of the integrated circuit die;
• a passivation layer disposed over the first side of the integrated circuit die, the passivation layer including an opening over each of the plurality of contact pads;
• a polymer layer disposed over the passivation layer, the polymer layer including a laser drilled opening over each of the plurality of contact pads;
• a molding material disposed around the integrated circuit die, the passivation layer, and the polymer layer, wherein a surface of the molding material is substantially co-planar with a surface of the polymer layer;
• a plurality of through-package vias (TPVs) disposed within the molding material;
• a redistribution layer (RDL) disposed over the molding material, the plurality of TPVs, and the polymer layer, wherein the RDL includes wiring that is coupled to each of the plurality of contact pads through the laser drilled openings in the polymer layer and the openings in the passivation layer;
• and
• an insulating material disposed over the second side of the integrated circuit die and the molding material, wherein the insulating material includes an opening over each of the plurality of TPVs.