Integrated circuits with aligned (100) NMOS and (110) PMOS FinFET sidewall channels
AssigneeTexas Instruments Incorporated
InventorsWeize W. Xiong, Cloves R. Cleavelin, Angelo Pinto, Rick L. Wise
Life of this patent
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Abstract
An integrated circuit device that includes a plurality of multiple gate FinFETs (MuGFETs) is disclosed. Fins of different crystal orientations for PMOS and NMOS MuGFETs are formed through amorphization and crystal regrowth on a direct silicon bonded (DSB) hybrid orientation technology (HOT) substrate. PMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having (110) crystal orientations. NMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having (100) crystal orientations in a Manhattan layout with the sidewall channels of the different PMOS and NMOS MuGFETs aligned at 0° or 90° rotations.
Claims20
An integrated circuit device, comprising:
- a first region of a semiconductor layer formed as a first fin having a top surface with a first crystal orientation and a sidewall surface with a second crystal orientation;
- and
- a second region of the layer formed as a second fin having a top surface with the second crystal orientation and a sidewall surface with the first crystal orientation;
- the first fin sidewall surface defining a channel with a first carrier flow direction of a first FinFET, the second fin sidewall defining a channel with a second carrier flow direction of a second FinFET, and the second carrier flow direction being parallel or perpendicular to the first carrier flow direction.
An integrated circuit device, comprising:
- a first region of a silicon layer formed as a first fin having a top surface with one of a (100) or (110) crystal orientation and a sidewall surface with the other of the (100) or (110) crystal orientation;
- and
- a second region of the layer formed as a second fin having a top surface with the other crystal orientation and a sidewall surface with the one crystal orientation;
- the first fin sidewall surface defining a channel with a current flow direction for one of an NMOS FinFET or a PMOS FinFET, the second fin sidewall surface defining a channel with current flow direction for the other of the NMOS FinFET or the PMOS FinFET, and the second current flow direction being parallel to the first current flow direction.
An integrated circuit, comprising:
- a first region of a silicon layer formed as a first fin having a sidewall surface with a (100) crystal orientation;
- a second region of the layer formed as a second fin having a sidewall surface with a (110) crystal orientation;
- and
- a third region of the layer formed as a third fin having a sidewall surface with a (100) crystal orientation;
- the first fin sidewall surface defining a channel for a first NMOS FinFET, the second fin sidewall surface defining a channel for a PMOS FinFET, and the third sidewall surface defining a channel for a second NMOS Fin FET, the first, second and third fin sidewall surfaces being generally parallel.
Dependencies are inferred from the claim text.