Memory device and display device equipped with memory device

A memory device comprising:

• a memory array in which memory cells are provided in a matrix pattern;
• a row driver which drives each row of the memory array;
• a column driver which drives each column of the memory array;
• a first wire which is provided for each row and connects memory cells in an identical row;
• a second wire and a third wire each of which connects the memory cells;
• and
• a fourth wire which is provided for each column and connects memory cells in an identical column, the fourth wire being driven by the column driver so that each of a first electric potential level and a second electric potential level each indicating a binary logic level is supplied to the fourth wire,
• the memory cells of the memory array each including:
• a switching circuit;
• a first retaining section;
• a transfer section;
• a second retaining section;
• and
• a first control section,
• the switching circuit being driven by the row driver via the first wire, so as to selectively turn on/off between the fourth wire and the first retaining section,
• the first retaining section retaining the binary logic level to be supplied thereto,
• the transfer section being driven via the second wire, so as to selectively carry out (i) a transfer operation in which the binary logic level retained in the first retaining section is transferred to the second retaining section in a state in which the binary logic level remains retained in the first retaining section and (ii) a non-transfer operation in which no transfer operation is carried out,
• the second retaining section retaining the binary logic level to be supplied thereto,
• the first control section being driven via the third wire, so as to be selectively controlled to be in a state in which the first control section carries out a first operation or a second operation,
• the first operation being an operation which is carried out by the first control section in (i) an active state in which the first control section receives an input thereto and supplies the input as an output thereof to the first retaining section or (ii) a non-active state in which the first control section stops carrying out an output, the active or non-active state having been selected in accordance with control information indicative of which of the first electric potential level and the second electric potential level is retained in the second retaining section as the binary logic level, and
• the second operation being an operation in which the first control section stops carrying out the output regardless of the control information;
• said memory device further including a voltage supply which supplies a set electric potential to an input of the first control section;
• and
• wherein in a reading mode in which the memory device reads the data from the memory cell, the memory device carries out a first step, a second step following the first step, and a third step following the second step,
• in the first step, in a state in which (i) the binary logic level which is equal to a level that is equivalent to the control information which causes the first control section to be in the active state is being supplied from the column driver to the fourth wire, (ii) the transfer section is carrying out the non-transfer operation, and (iii) the first control section is carrying out the second operation, the memory device causes the switching circuit to turn on, so as to write the binary logic level to the memory cell,
• in the second step, in a state in which (i) the switching circuit is on and (ii) the transfer section is carrying out the non-transfer operation, the memory device causes the first control section to carry out the first operation, and
• in the third step, in the state in which (i) the switching circuit is on and (ii) the transfer section is carrying out the non-transfer operation, the memory device causes the column driver to sense an electric potential of the fourth wire, so as to determine the data retained in the memory cell.

A memory device comprising:

• a memory array in which memory cells are provided in a matrix pattern;
• a row driver which drives each row of the memory array;
• a column driver which drives each column of the memory array;
• a first wire which is provided for each row and connects memory cells in an identical row;
• a second wire and a third wire each of which connects the memory cells;
• and
• a fourth wire which is provided for each column and connects memory cells in an identical column, the fourth wire being driven by the column driver so that each of a first electric potential level and a second electric potential level each indicating a binary logic level is supplied to the fourth wire,
• the memory cells of the memory array each including:
• a switching circuit;
• a first retaining section;
• a transfer section;
• a second retaining section;
• and
• a first control section,
• the switching circuit being driven by the row driver via the first wire, so as to selectively turn on/off between the fourth wire and the first retaining section,
• the first retaining section retaining the binary logic level to be supplied thereto,
• the transfer section being driven via the second wire, so as to selectively carry out (i) a transfer operation in which the binary logic level retained in the first retaining section is transferred to the second retaining section in a state in which the binary logic level remains retained in the first retaining section and (ii)a non-transfer operation in which no transfer operation is carried out,
• the second retaining section retaining the binary logic level to be supplied thereto,
• the first control section being driven via the third wire, so as to be selectively controlled to be in a state in which the first control section carries out a first operation or a second operation,
• the first operation being an operation which is carried out by the first control section in (i) an active state in which the first control section receives an input thereto and supplies the input as an output thereof to the first retaining section or (ii) a non-active state in which the first control section stops carrying out an output, the active or non-active state having been selected in accordance with control information indicative of which of the first electric potential level and the second electric potential level is retained in the second retaining section as the binary logic level,
• the second operation being an operation in which the first control section stops carrying out the output regardless of the control information,
• the first retaining section including a liquid crystal capacitor of a pixel electrode connected to the retaining node of the first retaining section, the retaining node retaining the binary logic level,
• the first wire serving also as a scanning signal line, and the fourth wire serving also as a data signal line, and
• the display device causing the row driver to drive the switching circuit via the first wire and supplying a data signal from the column driver via the fourth wire and the switching circuit to the first retaining section, so as to apply a voltage to the liquid crystal capacitor and to carry out a display,
• the display device carries out a first display mode in which the binary logic level is supplied as the data signal to the memory cell so that the display is carried out;
• said memory device further including a voltage supply which supplies a set electric potential to an input of the first control section;
• and
• wherein in the first display mode,
• the display device carries out a step A of (I) in a state in which (i) the binary logic level corresponding to the data signal is being supplied from the column driver to the fourth wire and (ii) the first control section is carrying out the second operation, causing the switching circuit to turn on, so as to write the binary logic level to the memory cell and (II) in a state in which (i) the binary logic level has been written to the memory cell and (ii) the first control section is carrying out the second operation, causing the transfer section to carry out the transfer operation;
• and
• the display device carries out, at least one time, a series of operations, which are a step B following the step A, a step C following the step B, and a step D following the step C, from the start of the step B to the end of the step D,
• in the step B, in a state in which (i) the first control section is carrying out the second operation and (ii) the transfer section is carrying out the non-transfer operation, the display device causes the switching circuit to turn on, so as to supply, to the first retaining section via the fourth wire, the binary logic level which is equal to a level that is equivalent to the control information which causes the first control section to be in the active state,
• in the step C, in a state in which (i) the switching circuit is off and (ii) the transfer section is carrying out the non-transfer operation, the display device causes the first control section to carry out the first operation, and by the time the first operation is finished, the display device causes the binary logic level to be supplied from the voltage supply to the input of the first control section, the binary logic level being inverse to the level that is equivalent to the control information which causes the first control section to be in the active state, and
• in the step D, in a state in which (i) the switching circuit is off and (ii) the first control section is carrying out the second operation, the display device causes the transfer section to carry out the transfer operation.

A memory device comprising:

• a memory array in which memory cells are provided in a matrix pattern;
• a row driver which drives each row of the memory array;
• a column driver which drives each column of the memory array;.
• a first wire which is provided for each row and connects memory cells in an identical row;
• a second wire and a third wire each of which connects the memory cells;
• and
• a fourth wire which is provided for each column and connects memory cells in an identical column, the fourth wire being driven by the column driver so that each of a first electric potential level and a second electric potential level each indicating a binary logic level is supplied to the fourth wire,
• the memory cells of the memory array each including:
• a switching circuit;
• a first retaining section;
• a transfer section;
• a second retaining section;
• and
• a first control section,
• the switching circuit being driven by the row driver via the first wire, so as to selectively turn on/off between the fourth wire and the first retaining section,
• the first retaining section retaining the binary logic level to be supplied thereto,
• the transfer section being driven via the second wire, so as to selectively carry out (i) a transfer operation in which the binary logic level retained in the first retaining section is transferred to the second retaining section in a state in which the binary logic level remains retained in the first retaining section and (ii) a non-transfer operation in which no transfer operation is carried out,
• the second retaining section retaining the binary logic level to be supplied thereto,
• the first control section being driven via the third wire, so as to be selectively controlled to be in a state in which the first control section carries out a first operation or a second operation,
• the first operation being an operation which is carried out by the first control section in (i) an active state in which the first control section receives an input thereto and supplies the input as an output thereof to the first retaining section or (ii) a non-active state in which the first control section stops carrying out an output, the active or non-active state having been selected in accordance with control information indicative of which of the first electric potential level and the second electric potential level is retained in the second retaining section as the binary logic level,
• the second operation being an operation in which the first control section stops carrying out the output regardless of the control information,
• the first retaining section including a liquid crystal capacitor of a pixel electrode connected to the retaining node of the first retaining section, the retaining node retaining the binary logic level,
• the first wire serving also as a scanning signal line, and the fourth wire serving also as a data signal line, and
• the display device causing the row driver to drive the switching circuit via the first wire and supplying a data signal from the column driver via the fourth wire and the switching circuit to the first retaining section, so as to apply a voltage to the liquid crystal capacitor and to carry out a display;
• said memory device further including a voltage supply which supplies a set electric potential to an input of the first control section;
• wherein the column driver is capable of supplying, to the fourth wire, a multilevel data signal which is the data signal whose electric potential levels are larger in number than the binary levels;
• and
• wherein the display device carries out a second display mode in which the multilevel data signal is supplied to the memory cell so that the display is carried out in a state in which the first control section does not carry out the first operation in which the first control section is in the active state.