Structure and method for FinFET integrated with capacitor

A semiconductor structure, comprising:

• a semiconductor substrate having a first region and a second region;
• a single fin active region formed on the semiconductor substrate that extends in the first and second regions;
• a shallow trench isolation (STI) feature formed in the semiconductor substrate and adjacent the fin active region, wherein the STI feature includes:
• a first portion disposed in the first region and a second portion disposed in the second region, and
• the first portion of the STI feature has a first top surface and the second portion of the STI feature has a second top surface higher than the first top surface;
• a first conductive feature formed on the fin active region and the STI feature, wherein the first conductive feature is disposed in the first region and covers the first portion of the STI feature, the first conductive feature further comprising a first width;
• a second conductive feature formed on the fin active region and the STI feature, wherein the second conductive feature is disposed in the second region, the second conductive feature further comprising a second width less than the first width;
• a first dielectric feature aligned with the first conductive feature and underlying the first conductive feature, the first dielectric feature comprising a first thickness;
• a second dielectric feature aligned with the second conductive feature and underlying the second conductive feature, the second dielectric feature comprising a second thickness different from the first thickness;
• wherein the fin active region, the first dielectric feature, and the first conductive feature are configured and coupled to form a capacitor;
• and
• wherein the fin active region, the second dielectric feature, and the second conductive feature are configured and coupled to form a field effect transistor.

A semiconductor structure, comprising:

• a semiconductor substrate having a first region and a second region;
• a shallow trench isolation (STI) feature formed in the semiconductor substrate, wherein the STI feature comprises a first portion disposed in the first region and having a first thickness T1 and a second portion disposed in the second region and having a second thickness T2 greater than the first thickness T1, the first portion of the STI feature being recessed from the second portion of the STI feature;
• a plurality of fin active regions on the semiconductor substrate;
• a plurality of conductive features disposed on the fin active regions and the STI feature,
• wherein one of the conductive features covers the first portion of the STI feature in the first region and a portion of the second portion of the STI feature in the second region;
• wherein the plurality of conductive features further comprise:
• a first conductive feature disposed in the first region and having a first width W1;
• and
• a second conductive feature disposed in the second region and having a second width W2 less than the first width W1;
• and
• a plurality of dielectric features underlying the conductive features and separating the conductive feature from the fin active regions, wherein the plurality of dielectric features comprise:
• a first dielectric feature disposed in the first region, underlying the first conductive feature, and having a first dielectric material;
• and
• a second dielectric feature disposed in the second region, underlying the second conductive feature, and having a second dielectric material different from the first dielectric material.

A semiconductor structure, comprising:

• a semiconductor substrate having a first region and a second region;
• a single fin active region formed on the semiconductor substrate that extends in the first and second regions;
• a shallow trench isolation (STI) feature formed in the semiconductor substrate and adjacent the fin active region, wherein the STI feature comprises:
• a first portion disposed in the first region and a second portion disposed in the second region, and
• the first portion of the STI feature has a first top surface and the second portion of the STI feature has a second top surface higher than the first top surface;
• a first conductive feature formed on the fin active region and the STI feature, wherein the first conductive feature is disposed in the first region and covers the first portion of the STI feature, the first conductive feature further comprising a first width;
• a second conductive feature formed on the fin active region and the STI feature, wherein the second conductive feature is disposed in the second region, the second conductive feature further comprising a second width less than the first width;
• a first dielectric feature aligned with the first conductive feature and underlying the first conductive feature, the first dielectric feature further comprising a first dielectric material;
• a second dielectric feature aligned with the second conductive feature and underlying the second conductive feature, the second dielectric feature further comprising a second dielectric material different from the first dielectric material;
• wherein the fin active region, the first dielectric feature, and the first conductive feature are configured and coupled to form a capacitor;
• and
• wherein the fin active region, the second dielectric feature, and the second conductive feature are configured and coupled to form a field effect transistor.