US 8,860,108 B2Granted

Oxide-based thin-film transistor (TFT) semiconductor memory device having source/drain electrode of one transistor connected to gate electrode of the other

AssigneeSemiconductor Energy Laboratory Co., Ltd.

InventorsShunpei Yamazaki, Jun Koyama, Kiyoshi Kato

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Abstract

It is an object to provide a semiconductor having a novel structure. In the semiconductor device, a plurality of memory elements are connected in series and each of the plurality of memory elements includes first to third transistors thus forming a memory circuit. A source or a drain of a first transistor which includes an oxide semiconductor layer is in electrical contact with a gate of one of a second and a third transistor. The extremely low off current of a first transistor containing the oxide semiconductor layer allows storing, for long periods of time, electrical charges in the gate electrode of one of the second and the third transistor, whereby a substantially permanent memory effect can be obtained. The second and the third transistors which do not contain an oxide semiconductor layer allow high-speed operations when using the memory circuit.

Claims16

Dependent claims

A semiconductor device comprising:

a first wiring;
a second wiring;
a third wiring;
a fourth wiring;
and
a fifth wiring,
wherein a plurality of memory elements are supported by a substrate including a semiconductor material, and connected in series between the first wiring and the second wiring, each memory element comprising:
a first transistor comprising a first gate electrode, a first source electrode, and a first drain electrode;
a second transistor comprising a second gate electrode, a second source electrode, and a second drain electrode;
and
a third transistor comprising a third gate electrode, a third source electrode, and a third drain electrode,
wherein the first gate electrode and one of the second source electrode and the second drain electrode are electrically connected to each other,
wherein the first wiring, the first source electrode, and the third source electrode are electrically connected to each other,
wherein the second wiring, the first drain electrode, and the third drain electrode are electrically connected to each other,
wherein the third wiring and the other of the second source electrode and the second drain electrode are electrically connected to each other,
wherein the fourth wiring and the second gate electrode are electrically connected to each other, and
wherein the fifth wiring and the third gate electrode are electrically connected to each other.

14 more elements

A semiconductor device comprising:

a first wiring;
a second wiring;
a third wiring;
a fourth wiring;
and
a fifth wiring,
wherein a plurality of memory elements are supported by a substrate including a semiconductor material, and connected in series between the first wiring and the second wiring, each memory element comprising:
a first transistor comprising a first gate electrode, a first source electrode, and a first drain electrode;
a second transistor comprising a second gate electrode, a second source electrode, and a second drain electrode;
and
a third transistor comprising a third gate electrode, a third source electrode, and a third drain electrode,
wherein the second transistor includes an oxide semiconductor layer,
wherein the first gate electrode and one of the second source electrode and the second drain electrode are electrically connected to each other,
wherein the first wiring, the first source electrode, and the third source electrode are electrically connected to each other,
wherein the second wiring, the first drain electrode, and the third drain electrode are electrically connected to each other,
wherein the third wiring and the other of the second source electrode and the second drain electrode are electrically connected to each other,
wherein the fourth wiring and the second gate electrode are electrically connected to each other, and
wherein the fifth wiring and the third gate electrode are electrically connected to each other.

15 more elements

A semiconductor device comprising:

a first wiring;
a second wiring;
a third wiring;
a fourth wiring;
and
a fifth wiring;
a substrate comprising a semiconductor material;
a first insulating layer over the substrate;
a second insulating layer over the first insulating layer;
embedded conductive layers embedded in the second insulating layer, the embedded conductive layers and the second insulating layer having a same thickness, and bottom surfaces of the embedded conductive layers coinciding with a bottom surface of the second insulating layer;
a third insulating layer over the second insulating layer and the embedded conductive layers;
wherein a plurality of memory elements are supported by the substrate, and connected in series between the first wiring and the second wiring, each memory element comprising:
a first transistor comprising a first gate electrode, a first source electrode, and a first drain electrode;
a second transistor comprising, a second gate electrode, a second source electrode, and a second drain electrode;
and
a third transistor comprising a third gate electrode, a third source electrode, and a third drain electrode,
wherein the second transistor includes an oxide semiconductor layer,
wherein the first gate electrode and one of the second source electrode and the second drain electrode are electrically connected to each other,
wherein the first wiring, the first source electrode, and the third source electrode are electrically connected to each other,
wherein the second wiring, the first drain electrode, and the third drain electrode are electrically connected to each other,
wherein the third wiring and the other of the second source electrode and the second drain electrode are electrically connected to each other,
wherein the fourth wiring and the second gate electrode are electrically connected to each other,
wherein the fifth wiring and the third gate electrode are electrically connected to each other,
wherein the first insulating layer is formed over the gate electrode of the first transistor;
wherein the second gate electrode is formed by one of the embedded conductive layers;
and
wherein the third insulating layer forms a gate insulating layer of the second electrode.

24 more elements

A semiconductor device comprising:

a first wiring;
a second wiring;
a third wiring;
a fourth wiring;
and
a fifth wiring;
a substrate comprising a semiconductor material;
a first insulating layer over the substrate;
a second insulating layer over the first insulating layer;
embedded conductive layers embedded in the second insulating layer, the embedded conductive layers and the second insulating layer having a same thickness, and bottom surfaces of the embedded conductive layers coinciding with a bottom surface of the second insulating layer;
a third insulating layer over the second insulating layer and the embedded conductive layers;
wherein a plurality of memory elements are supported by the substrate, and connected in series between the first wiring and the second wiring, each memory element comprising:
a first transistor comprising a first gate electrode, a first source electrode, and a first drain electrode;
a second transistor comprising, a second gate electrode, a second source electrode, and a second drain electrode;
and
a third transistor comprising a third gate electrode, a third source electrode, and a third drain electrode,
wherein the first gate electrode and one of the second source electrode and the second drain electrode are electrically connected to each other,
wherein the first wiring, the first source electrode, and the third source electrode are electrically connected to each other,
wherein the second wiring, the first drain electrode, and the third drain electrode are electrically connected to each other,
wherein the third wiring and the other of the second source electrode and the second drain electrode are electrically connected to each other,
wherein the fourth wiring and the second gate electrode are electrically connected to each other,
wherein the fifth wiring and the third gate electrode are electrically connected to each other,
wherein the first insulating layer is formed over the gate electrode of the first transistor;
wherein the second gate electrode is formed by one of the embedded conductive layers;
and
wherein the third insulating layer forms a gate insulating layer of the second electrode.

23 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/912,190Filed 26 Oct 2010
Priority: JP 2009-25127530 Oct 2009
Published: US 2011/0101334 A15 May 2011
Granted: 14 Oct 2014
Term ends: Not estimatedThe source records don’t support an estimate.

Classification13 codes

H10D 84/83
Of only field-effect components: of only insulated-gate FETs [IGFET]
G11C 11/404
With charge regeneration common to a multiplicity of memory cells, i.e. external refresh: with one charge-transfer gate, e.g. MOS transistor, per cell
G11C 11/405
With charge regeneration common to a multiplicity of memory cells, i.e. external refresh: with three charge-transfer gates, e.g. MOS transistors,…
G11C 16/02
Erasable programmable read-only memories: electrically programmable