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US 8,856,456 B2Granted
Systems, methods, and devices for cache block coherence
AssigneeApple Inc.
InventorsIan C. Hendry, Jeffry Gonion
Life of this patent
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Abstract
Systems, methods, and devices for efficient cache coherence between memory-sharing devices are provided. In particular, snoop traffic may be suppressed based at least partly on a table of block tracking entries (BTEs). Each BTE may indicate whether groups of one or more cache lines of a block of memory could potentially be in use by another memory-sharing device. By way of example, a memory-sharing device may employ a table of BTEs that each has several cache status entries. When a cache status entry indicates that none of a group of one or more cache lines could possibly be in use by another memory-sharing device, a snoop request for any cache lines of that group may be suppressed without jeopardizing cache coherence.
Claims28
A processor comprising:
- one or more processor cores configured to operate on cache lines from memory shared by another memory-sharing device;
- one or more caches configured to store a plurality of the cache lines;
- cache snoop circuitry comprising a table of cache block tracking entries, wherein each of the cache block tracking entries comprises a respective plurality of cache status entries, wherein each cache status entry respectively tracks a status of one or more of the cache lines, and wherein the cache snoop circuitry is configured, when one of the one or more processor cores requests one of the cache lines, to determine whether to issue a snoop request to the other memory-sharing device based at least in part on the table of cache block tracking entries;
- and
- a cache block coherence interface communicably interposed between the one or more processor cores and the another memory-sharing device, the cache block coherence interface having associated therewith a second table of cache block tracking entries, each block tracking entry of the second table of cache block tracking entries respectively tracking a possibly-shared status of each of a plurality of groups of one or more cache lines of a different block of memory, wherein the cache block coherence interface is configured to attempt to maintain cache coherence between the another memory-sharing device and the one or more processor cores based at least in part on the second table of cache block tracking entries.
2 more elements
A system comprising:
- two or more memory-sharing devices, each of the two or more memory-sharing devices respectively comprising a cache and a first table of block tracking entries, each of the block tracking entries of the table of block tracking entries being configured to track respective statuses of groups of cache lines of a block of memory;
- a memory device configured to be shared by the two or more memory-sharing devices;
- a communication bus configured to enable the two or more memory-sharing devices to issue snoop requests to one another;
- and
- a cache block coherence interface communicably interposed between the two or more memory-sharing devices, the cache block coherence interface having associated therewith a second table of cache block tracking entries, each block tracking entry of the second table of cache block tracking entries respectively tracking a possibly-shared status of each of a plurality of groups of one or more cache lines of a different block of memory, wherein the cache block coherence interface is configured to attempt to maintain cache coherence between the two or more memory-sharing devices based at least in part on the second table of cache block tracking entries;
- wherein each of the two or more memory-sharing devices is configured, upon receipt of a snoop request for a cache line not present in its cache, to issue a response comprising a block tracking entry that indicates respective statuses of groups of cache lines of a block of memory to which the requested cache line belongs, wherein the respective statuses of the groups of cache lines of the block of memory to which the requested cache line belongs are determined based at least in part on whether the cache lines of the block of memory to which the requested cache line belongs are present in its cache.
3 more elements
A system comprising:
- a memory device configured to store shared cache lines;
- a central processing unit configured to operate on the shared cache lines of the memory device, the central processing unit having associated therewith a first table of cache block tracking entries, each block tracking entry of the first table of cache block tracking entries respectively tracking a possibly-shared status of each of a plurality of groups of one or more cache lines of a different block of memory;
- and
- another memory-sharing device configured to operate on the shared cache lines of the memory device;
- wherein the central processing unit is configured to attempt to maintain cache coherence with the other memory-sharing device upon based at least in part on the first table of cache block tracking entries, wherein each block tracking entry of the first table of block tracking entries is configured to provide an indication of an amount of contention between the central processing unit and the other memory-sharing device for cache lines in the block of memory tracked by that block tracking entry, and a size of the block of memory respectively tracked by one of the block tracking entries of the first table of block tracking entries depends on the indication of the amount of contention provided by the one of the block tracking entries.
2 more elements
A method comprising:
- upon a cache miss of a desired cache line in a first processor of an electronic device, issuing a snoop request from the first processor to a second processor of the electronic device unless a valid block tracking entry of a first table of block tracking entries associated with the first processor, the valid block tracking entry tracking a block of memory that includes the desired cache line by way of a plurality of cache status entries each respectively associated with one or more cache lines of the block of memory, includes a cache status entry associated with the desired cache line that indicates that no snoop request is necessary to maintain cache coherence with the second processor;
- and
- determining in the first processor whether the second processor has not returned a response to the snoop request within a threshold amount of time and, when the second processor has not returned the response to the snoop request within the threshold amount of time, updating the first table of block tracking entries to indicate that all cache lines in a block of memory that includes the desired cache line should require a snoop request before being accessed.
Dependencies are inferred from the claim text.