Updating non-shadow registers in video encoder
AssigneeTexas Instruments Incorporated
InventorsPurushotam Kumar, Sivaraj Rajamonickam, Brijesh Rameshbhai Jadav, Manjunath Rudranna Hadli
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Abstract
A video processor controlled by a set of non-shadow registers is provided. A list of updates for one or more of the non-shadow registers may be prepared in a memory module. A frame buffer is updated with video data for a display coupled to the video processor. A blanking interval is detected after updating the frame buffer. A direct memory access engine is triggered to transfer the list of updates from the memory module to the non-shadow registers during the blanking interval.
Claims10
A method for operating a video processor having operations controlled by data stored in a set of non-shadow registers, data written into the non-shadow registers immediately effective in control of the video processor, the method comprising:
- preparing a list of updates in a memory module for one or more of the non-shadow registers;
- updating a frame buffer with video data for a display coupled to the video processor;
- detecting a blanking interval after updating the frame buffer;
- and
- triggering a direct memory access (DMA) engine to transfer the list of updates directly from the memory module to the non-shadow registers without intervention of shadow registers during the blanking interval.
A video system comprising:
- a video processor having operations controlled by data stored in a set of non-shadow registers, data written into the non-shadow registers immediately effective in control of the video processor;
- a video encoder coupled to receive video data from the video processor and having an output for coupling to a display device, wherein the video encoder is configured to update a frame buffer with video data for the display device, and further configured to assert a trigger signal in response to detecting a blanking interval after updating the frame buffer;
- and
- a direct memory access (DMA) engine coupled to a memory module and to the video processor, the DMA engine having a trigger input coupled to the trigger signal, wherein the DMA engine is configured to transfer a list of updates directly from the memory module to the non-shadow registers without intervention of shadow registers during the blanking interval when the trigger signal is asserted.
Dependencies are inferred from the claim text.