Video demodulation device

A video demodulation device configured to demodulate an RF signal resulting from analog modulation of a composite video, blanking, and sync signal (a CVBS signal) including a horizontal synchronizing signal, and to reproduce the CVBS signal by digital processing, the device comprising:

• a tuner configured to receive as input the RF signal resulting from analog modulation, and to output an analog IF signal;
• a demodulator configured to receive as input the analog IF signal, and to demodulate the CVBS signal, and
• a video processor configured to receive as input the demodulated CVBS signal, and to output a video signal by performing required processing, wherein
• the demodulator includes
• an analog-to-digital converter configured to convert the analog IF signal into a digital IF signal,
• an automatic phase controller configured to control and set a phase offset of a luminance component of the CVBS signal included in the digital IF signal to 0, and to output the digital IF signal as an audio/video signal,
• a filter configured to separate the audio/video signal into the luminance component, a color component, and an audio component, and to output the luminance component and the color component as a first CVBS signal,
• a luminance gain adjuster configured to perform gain adjustment of the luminance component included in the first CVBS signal such that a maximum of the luminance component found within a predetermined period becomes equal to a predetermined reference value, and to output the first CVBS signal as a second CVBS signal,
• a synchronization corrector configured to receive as input the second CVBS signal, to correct a signal corresponding to a signaling period of the horizontal synchronizing signal, and to output the second CVBS signal as a third CVBS signal,
• a clamp circuit configured to perform polarity inversion of the third CVBS signal, to adjust the third CVBS signal so as to be at a predetermined DC level, and to output the third CVBS signal as the CVBS signal, and
• a digital-to-analog converter configured to convert the CVBS signal having been input from the clamp circuit into an analog signal, and to output the analog signal to the video processor, and
• the synchronization corrector outputs, as the third CVBS signal, the second CVBS signal when the second CVBS signal is smaller than the reference value, or the reference value when the second CVBS signal is equal to or greater than the reference value.