Method for making a mask by forming a phase bar in an integrated circuit design layout
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsRu-Gun Liu, Shuo-Yen Chou, Hoi-Tou Ng, Ken-Hsien Hsieh, Yi-Yin Chen
Life of this patent
Estimating the term…
Abstract
A method for making a mask for an integrated circuit (IC) design includes receiving an IC design layout having a plurality IC features and performing a targeted-feature-surrounding (TFS) checking operation to identify a targeted-feature-surrounding-location (TFSL) in the IC design layout. The method also includes inserting a phase-bar (PB) to the TFSL, performing an optical proximity correction (OPC) to the IC design layout having the PB to form a modified IC design layout and providing the modified IC design layout for fabrication of the mask.
Claims20
A method for making a mask, comprising:
- receiving an integrated circuit (IC) design layout;
- performing a targeted-feature-surrounding (TFS) checking operation to identify a targeted-feature-surrounding-location (TFSL) in the IC design layout;
- inserting a phase bar (PB) to the TFSL;
- performing an optical proximity correction (OPC) to the IC design layout having the PB to form a modified IC design layout;
- and
- fabricating the mask based on the modified IC design layout.
A method of fabricating a mask, comprising:
- providing a substrate;
- providing an integrated circuit (IC) design layout having a phase-bar (PB);
- forming an absorption layer over the substrate, wherein the mask includes the substrate and the absorption layer;
- patterning the absorption layer to form an IC design layout pattern on the mask associated with the IC design layout therein, wherein the patterned absorption layer includes an opaque region and an absorber-absent region;
- and
- forming the PB in the absorber-absent region according to the IC design layout.
A method for making a mask, comprising:
- receiving an integrated circuit (IC) design layout;
- performing a targeted-feature-surrounding (TFS) checking operation to identify a targeted-feature-surrounding-location (TFSL) in the IC design layout;
- coincident with performing the TFS checking operation, generating a scattering bar (SB) table for the IC design layout;
- inserting a phase-bar (PB) to the TFSL in the IC design layout;
- inserting a SB in the IC design layout;
- performing an optical proximity correction (OPC) to the IC design layout having the PB and the SB to form a modified IC design layout;
- and
- fabricating the mask based on the modified IC design layout.
Dependencies are inferred from the claim text.