Back to results
US 8,847,683 B2Granted
Differential amplifying circuit
AssigneeFujitsu Limited
InventorNoriaki Shirai
Life of this patent
Estimating the term…
Abstract
A differential amplifying circuit includes: two metal oxide semiconductor transistors to form a differential pair and receive a differential signal; a plurality of capacitance elements coupled in series between drains of the two metal oxide semiconductor transistors; and an inductance circuit coupled between at least one connection node of the plurality of capacitance elements and a bias power terminal.
Claims9
A differential amplifying circuit comprising:
- two metal oxide semiconductor transistors to form a differential pair and receive a differential signal;
- a plurality of capacitance elements coupled in series between drains of the two metal oxide semiconductor transistors;
- and
- an inductance circuit coupled between at least one connection node of the plurality of capacitance elements and a bias power terminal,
- wherein an inductance value of the inductance circuit is variable,
- wherein the inductance circuit includes a plurality of inductance elements and a switching circuit to select at least one of the plurality of inductance elements.
3 more elements
A differential amplifying circuit comprising:
- two metal oxide semiconductor transistors to form a differential pair and receive a differential signal;
- a plurality of inductance elements coupled in series between drains of the two metal oxide semiconductor transistors;
- and
- a capacitance circuit coupled between at least one connection node of the plurality of inductance elements and a bias power terminal,
- wherein a capacitance value of the capacitance circuit is variable,
- wherein the capacitance circuit includes a plurality of capacitance elements and a switching circuit to select at least one of the plurality of capacitance elements.
3 more elements
A differential amplifying circuit comprising:
- two metal oxide semiconductor transistors to form a differential pair and receive a differential signal;
- a plurality of capacitance elements coupled in series between drains of the two metal oxide semiconductor transistors;
- an inductance circuit coupled between at least one connection node of the plurality of capacitance elements and a bias power terminal,
- a first load element coupled between at least one of the drains of the two metal oxide semiconductor transistors and one of a high-potential power terminal and a low-potential power terminal;
- and
- a second load element coupled between a connection node of sources of the two metal oxide semiconductor transistors and the other of the high-potential power terminal and the low-potential power terminal.
3 more elements
Dependencies are inferred from the claim text.