Minute transistor

A memory device comprising:

• a first transistor comprising a first semiconductor material, a first gate electrode layer, a first gate insulating layer interposed between the first semiconductor material and the first gate electrode layer, a first source electrode layer and a first drain electrode layer electrically connected to the first semiconductor material;
• a first insulating layer over the first semiconductor material;
• a second transistor comprising a second semiconductor material in a semiconductor layer over the first insulating layer, the second transistor further comprising:
• a second gate insulating layer over the semiconductor layer;
• a second gate electrode layer over the semiconductor layer with the second gate insulating layer interposed therebetween;
• a second insulating layer over the second gate insulating layer, the second insulating layer comprising a first opening and a second opening each formed from a top surface to a bottom surface of the second insulating layer;
• a second source electrode layer and a second drain electrode layer respectively embedded in the first opening and the second opening so that side surfaces of the second source electrode layer and the second drain electrode layer are in contact with the second insulating layer, each of the second source electrode layer and the second drain electrode layer being on and in contact with the semiconductor layer;
• and
• a source wiring layer and a drain wiring layer respectively on and in contact with the second source electrode layer and the second drain electrode layer,
• wherein the first gate electrode layer is in electrical contact with one of the second source electrode layer and the second drain electrode layer, and
• wherein, in the second transistor, a distance in a channel formation region length direction between the second source electrode layer and the second drain electrode layer is shorter than a distance in the channel formation region length direction between the source wiring layer and the drain wiring layer.