Apparatus, method, and system for implementing micro page tables

A method comprising:

• storing one or more memory page address translations between linear addresses and platform physical addresses in a translation lookaside buffer (TLB), wherein the platform physical addresses map to micro physical addresses of a memory;
• storing entries in a page miss handler tag table to index platform physical addresses to micro physical addresses, wherein each entry, in addition to an index indexing a platform physical address to a micro physical address, includes state information of a memory page associated with the micro physical address;
• implementing rank shedding of the memory, including updating the state information in the page miss handler tag table to reflect results of rank shedding related operations performed on the memory;
• receiving a memory page request for a memory page in the memory, the memory page request including a linear address;
• in response to the memory page request, searching the TLB to locate the corresponding platform physical address that maps to a micro physical address of the memory;
• and
• in response to the TLB not storing the memory page address translation for the memory page referenced by the memory page request, searching the page miss handler tag table to obtain updates for the TLB.

A non-transitory machine-readable medium having stored thereon instructions, which if executed by a machine, cause the machine to:

• store one or more memory page address translations between linear addresses and platform physical addresses in a translation lookaside buffer (TLB), wherein the platform physical addresses map to micro physical addresses of a memory;
• store entries in a page miss handler tag table to index platform physical addresses to micro physical addresses, wherein each entry, in addition to an index indexing a platform physical address to a micro physical address, includes state information of a memory page associated with the micro physical address;
• implement rank shedding of the memory, including updating the state information in the page miss handler tag table to reflect results of rank shedding related operations performed on the memory;
• receive a memory page request for a memory page in the memory, the memory page request including a linear address;
• in response to the memory page request, search the TLB to locate the corresponding platform physical address that maps to a micro physical address of the memory;
• and
• in response to the TLB not storing the memory page address translation for the memory page referenced by the memory page request, search the page miss handler tag table to obtain updates for the TLB.

A system, comprising:

• a memory, wherein the memory includes a hidden portion for storing at least a page miss handler tag table configured to store a plurality of entries configured to index platform physical addresses to micro physical addresses of the memory, wherein each entry, in addition to an index indexing a platform physical address to a micro physical address, includes state information of a memory page associated with the micro physical address;
• and
• a processor, the processor including:
• logic to receive a memory page request for a memory page, wherein the memory page request includes a linear address of the memory page;
• a translation lookaside buffer (TLB) to store one or more memory page address translations configured to translate linear addresses to platform physical addresses;
• a page miss handler logic to perform a micro physical address lookup in the page miss handler tag table in response to the TLB not storing the memory page address translation for the memory page referenced by the memory page request;
• and
• a memory management logic to implement rank shedding of the memory, including updating the state information in the entries of the page miss handler tag table to reflect results of rank shedding related operations performed on the memory.