Method of operating semiconductor memory device with floating body transistor using silicon controlled rectifier principle

A semiconductor memory cell comprising:

• a floating body region configured to be charged to a level indicative of a state of the memory cell;
• a first region in electrical contact with said floating body region;
• a second region in electrical contact with said floating body region and spaced apart from said first region;
• a gate positioned between said first and second regions;
• a buried layer region in electrical contact with said floating body region, below said first and second regions, spaced apart from said first and second regions;
• and
• a substrate region positioned below said buried layer region;
• wherein applying a voltage to said substrate region results in at least two stable floating body charge levels.

A semiconductor memory array comprising:

• a plurality of said memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell includes:
• a floating body region configured to be charged to a level indicative of a state of the memory cell;
• a first region in electrical contact with said floating body region;
• a second region in electrical contact with said floating body region and spaced apart from said first region;
• a gate positioned between said first and second regions;
• a buried layer region in electrical contact with said floating body region, below said first and second regions, spaced apart from said first and second regions;
• and
• a substrate region;
• wherein said substrate region is commonly connected to at least two of said memory cells, and wherein said substrate region is configured to inject charge into said floating body region of each of said memory cells connected thereto, to maintain said state of the memory cells in parallel.