Bit error rate based wear leveling for solid state drive memory
AssigneeInternational Business Machines Corporation
InventorsThomas J. Griffin, Dustin J. Vanstee
Life of this patent
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Abstract
According to exemplary embodiments, a system, method, and computer program product are provided for BER-based wear leveling in a SSD. A block-level BER value for a block in the SSD is determined. An adjusted PE cycle count for the block is incremented or decremented based on the block-level BER value. Wear leveling is then performed in the SSD based on the adjusted PE cycle count.
Claims18
A method for bit error rate (BER) based wear leveling in a solid state drive (SSD), the method comprising:
- determining a block-level BER value for a block in the SSD;
- incrementing or decrementing an adjusted program/erase (PE) cycle count for the block based on the block-level BER value by a processor;
- and
- performing wear leveling in the SSD based on the adjusted PE cycle count by distributing PE cycling among a plurality of blocks in the SSD based on a respective adjusted PE cycle count of each of the plurality of blocks in the SSD.
A computer program product for bit error rate (BER) based wear leveling in a solid state drive (SSD), the computer program product comprising:
- a tangible non-transitory storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:
- determining a block-level BER value for a block in the SSD;
- incrementing or decrementing an adjusted program/erase (PE) cycle count for the block based on the block-level BER value by a processor;
- and
- performing wear leveling in the SSD based on the adjusted PE cycle count by distributing PE cycling among a plurality of blocks in the SSD based on a respective adjusted PE cycle count of each of the plurality of blocks in the SSD.
Dependencies are inferred from the claim text.