Synchronizing multiple threads efficiently
AssigneeIntel Corporation
InventorsSailesh Kottapalli, John H. Crawford
Life of this patent
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Abstract
In one embodiment, the present invention includes a method of assigning a location within a shared variable for each of multiple threads and writing a value to a corresponding location to indicate that the corresponding thread has reached a barrier. In such manner, when all the threads have reached the barrier, synchronization is established. In some embodiments, the shared variable may be stored in a cache accessible by the multiple threads. Other embodiments are described and claimed.
Claims13
A processor comprising:
- a first processor core;
- a second processor core coupled to the first processor core;
- a shared cache coupled to the first processor core and the second processor core to store a plurality of thread synchronization variables;
- and
- logic, responsive to a fetchset instruction comprising a single instruction of an instruction set architecture, to overwrite a thread synchronization variable stored in the shared cache while a cache line including the plurality of thread synchronization variables is prevented from being copied into either of the first and second processor cores when a corresponding one of a plurality of threads reaches a barrier, wherein each of the plurality of thread synchronization variables is to indicate a synchronization status for one of the plurality of threads at the barrier.
A non-transitory machine-readable medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:
- receiving a single instruction of an instruction set architecture in a first processor, wherein the single instruction comprises a fetchset instruction;
- responsive to the single instruction, reading a shared variable having a location for each of multiple threads, the shared variable stored in a shared last level cache coupled to the first processor and a second processor;
- and
- further responsive to the single instruction, writing a value to a corresponding location within the shared variable assigned to a first thread to indicate that the first thread reached a barrier while a cache line including the shared variable is prevented from being copied into either of the first and second processors, the shared variable to indicate a synchronization status for the multiple threads at the barrier and each location within the shared variable readable by all of the multiple threads but only writable by one of the multiple threads.
A processor comprising:
- a first processor core;
- a second processor core;
- and
- a last level cache memory coupled to the first and second processor cores, wherein the last level cache memory is to store a first shared variable including a plurality of portions each corresponding to a thread of a plurality of threads, wherein the first processor core is to perform a single fetchset instruction of a first instruction set architecture to overwrite a first portion of the first shared variable while a cache line including the first shared variable is prevented from being copied into either of the first and second processor cores when a corresponding one of the plurality of threads reaches a barrier.
Dependencies are inferred from the claim text.