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US 8,819,614 B2Granted
ESD analysis apparatus
AssigneeKabushiki Kaisha Toshiba
InventorSachio Hayashi
Life of this patent
Estimating the term…
Abstract
According to one embodiment, a chip model generating unit and a counter tester ground capacitance adding unit are provided. The chip model generating unit generates a chip model based on an ESD protection circuit network model to which an inter power net capacitance of a semiconductor chip is added. The counter tester ground capacitance adding unit adds a counter tester ground capacitance to the chip model.
Claims17
An ESD analysis apparatus, comprising:
- a chip model generating unit that generates a chip model based on an ESD protection circuit network model to which an inter power net capacitance of a semiconductor chip is added;
- a package model generating unit that generates a package model based on an equivalent circuit model to which an inter power net capacitance of a semiconductor package including the semiconductor chip mounted therein is added;
- a counter tester ground capacitance adding unit that adds a counter tester ground capacitance to the chip model and the package model;
- a CDM analysis netlist generating unit that generates a CDM analysis netlist based on a connection relation between the chip model, the package model, and a tester model;
- a transient analysis unit that performs transient analysis of an equivalent circuit generated based on the CDM analysis netlist;
- and
- a maximum potential difference output unit that outputs a maximum potential difference between nodes disposed in the equivalent circuit in the transient analysis,
- wherein the chip model generating unit includes
- a core portion modeling unit that models a core portion of the semiconductor chip by a resistive network,
- an IO portion modeling unit that generates the ESD protection circuit network model based on a connection state between an electrostatic protection element of the IO portion of the semiconductor chip and the resistive network, and
- a first inter power net capacitance adding unit that adds an inter power net capacitance of the core portion to the resistive network and adds an inter power net capacitance of the IO portion to the ESD protection circuit network model, and
- the package model generating unit includes
- an RL modeling unit that models an interconnection of the semiconductor package by a connection relation between a resistor and an inductor, and
- a second inter power net capacitance adding unit that adds the inter power net capacitance of the semiconductor package between power nets described by the connection relation between the resistor and the inductor.
11 more elements
An ESD analysis apparatus, comprising:
- a chip model generating unit that generates a chip model based on an ESD protection circuit network model to which an inter power net capacitance of a semiconductor chip is added;
- a package model generating unit that generates a package model based on an equivalent circuit model to which an inter power net capacitance of a semiconductor package including the semiconductor chip mounted therein is added;
- a first counter tester ground capacitance adding unit that adds a counter tester ground capacitance to the chip model a second counter tester ground capacitance adding unit that adds a counter tester ground capacitance to the package model;
- a CDM analysis netlist generating unit that generates a CDM analysis netlist based on a connection relation between the chip model, the package model, and a tester model;
- a transient analysis unit that performs transient analysis of an equivalent circuit generated based on the CDM analysis netlist;
- a maximum potential difference output unit that outputs a maximum potential difference between nodes disposed in the equivalent circuit in the transient analysis,
- wherein the chip model generating unit includes
- a core portion modeling unit that models a core portion of the semiconductor chip by a resistive network,
- an IO portion modeling unit that generates the ESD protection circuit network model based on a connection relation between an electrostatic protection element of the IO portion of the semiconductor chip and the resistive network, and
- a first inter power net capacitance adding unit that adds an inter power net capacitance of the core portion to the resistive network and adds an inter power net capacitance of the IO portion to the ESD protection circuit network model.
7 more elements
Dependencies are inferred from the claim text.