Analyzing timing requirements of a hierarchical integrated circuit design
AssigneeInternational Business Machines Corporation
InventorTimothy D. Helvey
Life of this patent
Estimating the term…
Abstract
Logic gates in a child unit of a hierarchical integrated circuit design that are visible in an abstract model of the child unit of the hierarchical integrated circuit design are marked. A hide bit is set for the marked logic gates and a modification on the child unit is performed. The marked logic gates in the child unit are preserved during modification of the child unit. The hide bit is cleared from each marked logic gate and the logic gates are unmarked when modification of the child unit is complete.
Claims20
A computer-implemented method for analyzing timing requirements of a hierarchical integrated circuit design having a plurality of child units, the method comprising:
- accessing a netlist having a plurality of logic gates of a child unit from the plurality of child units;
- determining a set of logic gates are members of both the plurality of logic gates of the child unit and a plurality of logic gates of an abstract model of the child unit;
- marking the set of logic gates, based on the determination, such that an integrated circuit modification process recognizes the set of logic gates;
- executing the integrated circuit modification process on the child unit, such that at least one logic gate from the child unit is changed;
- preserving the set of marked logic gates, in response to the marking, such that the set of logic gates are unchanged by the integrated circuit modification process;
- and
- generating a new child unit in response to the integrated circuit modification process.
A system for analyzing timing requirements of a hierarchical integrated circuit design having a plurality of child units, the system comprising:
- a timing tool configured to:
- access a netlist having a plurality of logic gates of a child unit from the plurality of child units,
- determine a set of logic gates are members of both the plurality of logic gates of the child unit and a plurality of logic gates of an abstract model of the child unit,
- mark the set of logic gates, based on the determination, such that an integrated circuit modification process recognizes the set of logic gates, and
- preserve the set of marked logic gates, in response to the marking, such that the set of logic gates are unchanged by the integrated circuit modification process;
- and
- an optimization tool configured to:
- execute the integrated circuit modification process on the child unit, such that at least one logic gate from the child unit is changed, and
- generate a new child unit in response to the integrated circuit modification process.
A computer program product configured to analyze timing requirements of a hierarchical integrated circuit design having a plurality of child units, the computer program product comprising a computer readable storage medium having program code embodied therewith, the program code comprising computer readable program code configured to:
- access a netlist having a plurality of logic gates of a child unit from the plurality of child units;
- determine a set of logic gates are members of both the plurality of logic gates of the child unit and a plurality of logic gates of an abstract model of the child unit;
- mark the set of logic gates, based on the determination, such that an integrated circuit modification process recognizes the set of logic gates;
- execute the integrated circuit modification process on the child unit, such that at least one logic gate from the child unit is changed;
- preserve the set of marked logic gates, in response to the marking, such that the set of logic gates are unchanged by the integrated circuit modification process;
- and
- generate a new child unit in response to the integrated circuit modification process, such that the new child unit includes the set of preserved marked logic gates and the at least one changed logic gate.
Dependencies are inferred from the claim text.