Designing integrated circuits for high thermal reliability

A computer-implemented method, comprising:

• continually testing a functional test block associated with each of one or more functional blocks within a hardware device;
• powering down a circuitry in a functional block of the hardware device on test failure of an associated functional test block;
• and
• powering up a circuitry in the functional block of the hardware device on test passage of the associated functional test block.

A system, comprising:

• a circuitry organized in one or more functional block(s) implemented with a first group of one or more timing constraint value(s), wherein a controller is operable to power down selective components of the circuitry;
• one or more functional test block(s) operable to selectively replicate the circuitry implemented with a second group of one or more timing constraint value(s), wherein the second group of timing constraint value(s) are less stringent than the first group of timing constraint value(s);
• and
• a built-in self-test (BIST) circuitry operable to test the one or more functional test block(s), wherein the BIST circuitry is implemented with the first group of timing constraint value(s);
• wherein the BIST circuitry is further operable to communicate a BIST status to the controller, wherein the controller is implemented with the first group of timing constraint value(s);
• and
• wherein the controller is further operable to initiate the BIST circuitry and selectively power down the circuitry on failure of the BIST circuitry.