Memory circuits and methods of making and designing the same

A method, comprising:

• receiving a source SRAM cell having at least two pull-up transistors, at least two pull-down transistors, and at least pass gate transistors, each of the transistors having a drawn size, each of the transistors being a conventional MOS transistor;
• generating a target SRAM cell by replacing one or more of the conventional MOS transistors in the received SRAM cell with a replacement transistor having a reduced threshold voltage variation as compared to the corresponding conventional transistor, the replacement transistor having a drawn gate size that is substantially identical to that of the corresponding conventional transistor;
• determining base minimum supply voltage and a corresponding base failure rate of the conventional SRAM cell, the base minimum supply voltage being a lowest supply voltage at which a predetermined percentage of the SRAM cells can correctly perform read and write operations, the failure rate corresponding to the percentage of SRAM cells that fail at the base minimum supply voltage;
• determining at least one base threshold voltage (Vt) of at least one transistor in the target SRAM cell, and a base supply voltage for the target SRAM cell;
• and
• modifying the target SRAM cell to generate a target SRAM cell having a lower base minimum supply voltage, the steps for modifying further comprising:
• (i) determining one or more candidate failure rates of a group of the target SRAM cells in response to one or more modified threshold voltage candidate values of the at least one transistor, the candidate failure rates being determined for the base minimum power supply voltage;
• if the failure rate for one of the modified threshold voltage values is lower than the base failure rate, saving the one modified threshold voltage candidate value as the base threshold voltage value and returning to (i);
• if the failure rate for one of more of the modified threshold voltage values is not lower than the base failure rate, but is lower than a predetermined target failure rate, reducing the base minimum supply voltage by a predetermined voltage step, and returning to (i);
• and
• if the failure rate for one or more of the modified threshold voltage candidate values is greater than a failure limit, saving the current threshold voltage value and base minimum power supply voltage as target features of the target SRAM cell.