Hierarchical verification of clock domain crossings

A method for performing hierarchical clock domain crossing verification using a computer system, the method comprising:

• using the computer system to access a device design having block-level group of design blocks and a top-level group of design blocks, each of the block-level group and the top-level group including a plurality of asynchronous clocks;
• initiating a first clock domain crossing verification process for one or more design blocks of the block-level group to generate interface modeling information;
• initiating a second clock domain crossing verification process for the top-level group utilizing the interface modeling information to verify one or more clock domain crossings between the block-level group and the top-level group;
• and
• reporting one or more clock domain crossing violations.

A method for performing hierarchical clock domain crossing verification using a computer system, the method comprising:

• using the computer system to access a device design having a top-level, a plurality of design blocks, and a plurality of asynchronous clocks;
• dividing the device design into a partitioned device design having a block-level group including one or more first design blocks of the plurality of design blocks and a top-level group including one or more second design blocks of the plurality of design blocks;
• performing a first clock domain crossing verification process on each design block of the one or more first design blocks to generate interface modeling information corresponding with each design block;
• performing a second clock domain crossing verification process on the top-level, each of the first design blocks being represented by the corresponding interface modeling information;
• and
• reporting one or more clock domain crossing violations.