Systems and methods for mitigating stubborn errors in a data processing system
AssigneeLSI Corporation
InventorsHaitao Xia, Wu Chang, Shaohua Yang
Life of this patent
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Abstract
Various embodiments of the present invention provide data processing circuits that include: a data detector circuit, a data decoder circuit, and a modification circuit. The data detector circuit is operable to apply a data detection algorithm to a data input to yield a detected output. The data decoder circuit is operable to apply a data decode algorithm to a decode input to yield a decoded output. The decode input is selected between at least the detected output, and a modified version of the detected output. The modification circuit is operable to receive the detected output and to provide the modified version of the detected output.
Claims20
A data processing circuit, the data processing circuit 1 comprising:
- a data detector circuit operable to apply a data detection algorithm to a data input to yield a detected output;
- a data decoder circuit operable to apply a data decode algorithm to a decode input to yield a decoded output, wherein the decode input is selectable between the detected output, and a modified version of the detected output;
- and
- a modification circuit operable to receive the detected output and to provide the modified version of the detected output, wherein the modification circuit includes a comparator circuit configured to compare the detected output with an identified pattern.
A method for data processing, the method comprising:
- using a data detector circuit to apply a data detection algorithm to a data input to yield a detected output;
- using a data decoder circuit to apply a data decode algorithm to a decode input to yield a decoded output;
- and
- selecting between the detected output and a modified version of the detected output to provide as the decode input, wherein selecting between the detected output and the modified version of the detected output includes comparing hard decisions of the detected output with an identified pattern, wherein the modified version of the detected output is provided as the decode input based at least in part on a match between the hard decisions of the detected output and the identified pattern.
A storage device, the storage device comprising:
- a storage medium;
- a head assembly disposed in relation to the storage medium and operable to provide a sensed signal corresponding to information on the storage medium;
- a read channel circuit including:
- an analog processing circuit operable to provide an analog signal corresponding to the sensed signal;
- an analog to digital converter circuit operable to sample the analog signal to yield a series of digital samples;
- an equalizer circuit operable to equalize the digital samples to yield an equalized input;
- a data detector circuit operable to apply a data detection algorithm to the equalized input to yield a detected output;
- a data decoder circuit operable to apply a data decode algorithm to a decode input to yield a decoded output, wherein the decode input is selected from a group consisting of:
- the detected output, and a modified version of the detected output;
- and
- a modification circuit operable to receive the detected output and to provide the modified version of the detected output.
Dependencies are inferred from the claim text.