Apparatus and method for decoding low density parity check coded signals

An apparatus comprising:

• a means for reading data from a first memory, said data being arranged in an initial configuration;
• a means for forward shifting said data from the first memory, said means for forward shifting arranging said data in a second configuration;
• a means for processing said forward shifted data using a first portion of an error correction process;
• a means for reverse shifting said processed data, said means for reverse shifting returning said processed data from said second configuration to said initial configuration returning said first processed data to said initial configuration, said means for reverse shifting including a means for bypassing said reverse shifting if said processed data is an intermediate result;
• means for writing said intermediate result into a second memory if said processed data is an intermediate result;
• and a means for writing said reverse shifted data into said first memory if said processed data is not an intermediate result, wherein said reverse shifted data in said initial configuration is a configuration used for processing in a second portion of an error correction process and wherein said first memory receives a signal containing data bits and error correction bits from a carrier tracking loop and outputs a signal containing error corrected data bits to an interleaver and only stores data in said initial configuration.