Mixed domain FFT-based non-binary LDPC decoder
AssigneeLSI Corporation
InventorsLei Chen, Zongwang Li, Johnson Yen, Shaohua Yang
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Abstract
Various embodiments of the present invention are related to methods and apparatuses for decoding data, and more particularly to methods and apparatuses for decoding data in a mixed domain FFT-based non-binary LDPC decoder. For example, in one embodiment an apparatus includes a message processing circuit operable to process variable node messages and check node messages in a log domain, and a check node calculation circuit in the low density parity check decoder operable to perform a Fast Fourier Transform-based check node calculation in a real domain. The message processing circuit and the check node calculation circuit perform iterative layer decoding.
Claims20
An apparatus for non-binary decoding of low density parity check encoded data comprising:
- a message processing circuit in a low density parity check decoder operable to process variable node messages and check node messages in a log domain;
- a check node calculation circuit in the low density parity check decoder operable to perform a Fast Fourier Transform-based check node calculation in a real domain, wherein the check node calculation circuit comprises:
- a Fast Fourier Transform circuit operable to perform a Fast Fourier Transform on variable node values for a current layer in the real domain:
- a first inverse Fast Fourier Transform circuit operable to perform an inverse Fast Fourier Transform to yield check node values for a connected layer in the real domain;
- and
- a second inverse Fast Fourier Transform circuit operable to perform an inverse Fast Fourier Transform to yield check node values for the current layer in the real domain;
- and
- wherein the message processing circuit and the check node calculation circuit are operable to perform iterative layer decoding.
A method of decoding data in a mixed domain non-binary low density parity check decoder, comprising:
- processing variable node messages and check node messages in the mixed domain low density parity check decoder in a log domain;
- transforming variable node messages from the log domain to a real domain;
- performing Fast Fourier Transform-based check node calculations on variable node values for a current layer in the real domain, wherein the processing and the check node calculations comprise iterative layer decoding;
- performing an inverse Fast Fourier Transform to yield check node values for a current layer in the real domain;
- performing an inverse Fast Fourier Transform to yield check node values for a connected layer in the real domain;
- and
- transforming the real domain check node values for the current layer and for the connected layer from the real domain to the log domain.
A storage system comprising:
- a storage medium maintaining a data set;
- a write head operable to magnetically record the data set to the storage medium;
- and
- a mixed domain non-binary low density parity check decoder operable to perform layered decoding, comprising:
- a message processing circuit operable to process variable node messages and check node messages in a log domain;
- and
- a check node calculation circuit operable to perform a Fast Fourier Transform-based check node calculation in a real domain, wherein the check node calculation circuit comprises:
- a Fast Fourier Transform circuit operable to perform a Fast Fourier Transform on variable node values for a current layer in the real domain;
- a first inverse Fast Fourier Transform circuit operable to perform an inverse Fast Fourier Transform to yield check node values for a connected layer in the real domain;
- and
- a second inverse Fast Fourier Transform circuit operable to perform an inverse Fast Fourier Transform to yield check node values for the current layer in the real domain.
Dependencies are inferred from the claim text.