Methods and systems for an automated test configuration to identify logic device defects
AssigneeAdvanced Micro Devices, Inc.
InventorAngel Socarras
Life of this patent
Estimating the term…
Abstract
Provided is an apparatus configured for testing a logic device. The apparatus includes a testing mechanism configured to output test patterns representative of logical structures within the logic device and a testable logic device having (i) input ports coupled to output ports of the automated testing mechanism and (ii) output ports coupled to input ports of the automated testing mechanism. The apparatus also includes a fusing mechanism configured to compensate for defects within the logic device responsive to a segregation of the type of defects identified.
Claims20
An apparatus, comprising:
- a testing mechanism configured to simultaneously output multiple test patterns representative of different sections of logical structures within a testable logic device, provide the multiple test patterns to separate scan chains of the testable logic device, and compare the multiple test patterns with results produced from the separate scan chains to identify defects within interconnected logic sub-modules of the different sections of the testable logic device;
- a testable logic device having input ports coupled to output ports of the testing mechanism and output ports coupled to input ports of the testing mechanism;
- and
- a fusing mechanism configured to compensate for defects within the sub-modules of the different sections of the testable logic device responsive to a segregation of the type of defects identified.
A fusing mechanism comprising:
- internal circuitry configured to facilitate tracking defects in logical structures within sub-modules of different sections of a logic device;
- wherein the fusing mechanism is connectable to the logic device and a tester configured to transmit multiple test patterns for testing the sub-modules of the different sections of the logic device.
A method for testing a logic device, comprising:
- simultaneously producing multiple test patterns representative of different sections of logical structures within the logic device via a testing mechanism;
- inputting the multiple testing patterns into separate scan chains of the logic device;
- comparing the multiple test patterns with results produced from the separate scan chains to identify defects within interconnected logic sub-modules of the different sections of the logic device;
- and
- compensating for the defects via a fusing mechanism, the compensating being responsive to a segregation of the type of defects identified.
Dependencies are inferred from the claim text.