Scan test circuitry configured to prevent violation of multiplexer select signal constraints during scan testing

A processing system comprising:

• a processor;
• and
• a memory coupled to the processor and configured to store information characterizing an integrated circuit design;
• wherein the processing system is configured to provide scan test circuitry within the integrated circuit design, the integrated circuit design comprising:
• a decoder having a plurality of select signal outputs;
• and
• a multiplexer having a plurality of select signal inputs subject to a specified select signal constraint, wherein the select signal constraint indicates that if a given one of the plurality of select signal inputs receives a select signal at a particular logic level, one or more other ones of the plurality of select signal inputs receive respective select signals at another logic level;
• the scan test circuitry comprising at least one scan chain having a plurality of scan cells coupled between respective ones of the select signal outputs of the decoder and respective ones of the select signal inputs of the multiplexer;
• the scan test circuitry being configured to control at least a given one of the scan cells so as to prevent violation of the select signal constraint in conjunction with scan testing.