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US 8,819,505 B2Granted
Data processor having disabled cores
AssigneePact Xpp Technologies AG
InventorsMartin Vorbach, Robert Münch
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Abstract
A data processor having a plurality of data processing cores configured to disable cores found defective by a self-test.
Claims52
An Integrated Circuit Data Processor, comprising:
- data processing cores being arranged in an array;
- a plurality of the data processing cores comprising at least one Arithmetic and Logic Unit;
- and
- wherein the integrated circuit is operative to:
- perform at least a self-test on the plurality of data processing cores comprising at least one Arithmetic and Logic Unit;
- and
- disable data processing cores found by the self-test to be defective.
4 more elements
An Integrated Circuit Data Processor, comprising:
- data processing cores arranged in an array;
- a plurality of the data processing cores comprise at least one Arithmetic Logic Unit;
- and
- at least some of the data processing cores operative to process different instructions at a single time;
- and
- a non-volatile memory;
- wherein, if at least one core is determined to be a defective core:
- the non-volatile memory is operative to store information representing the defective data processing cores;
- and
- at least some of the plurality of data processing cores are capable of being switched-off as function of the information representing the defective data processing cores.
7 more elements
An Integrated Circuit Data Processor, comprising:
- data processing cores arranged in an array;
- a plurality of the data processing cores comprise at least one Arithmetic Logic Unit;
- and
- at least some of the data processing cores operative to process different instructions at a single time;
- and
- a non-volatile memory;
- wherein, if at least one core is determined to be a defective core:
- the non-volatile memory is operative to store information representing the defective data processing cores;
- and
- at least some of the plurality of data processing cores are switched-off as function of the information representing the defective data processing cores.
7 more elements
An Integrated Circuit Data Processor, comprising:
- data processing cores arranged in an array;
- a plurality of the data processing cores comprise at least one Arithmetic Logic Unit;
- and
- at least some of the data processing cores operative to process different instructions at a single time;
- an interconnection system to which the plurality of data processing cores are connected;
- and
- a non-volatile memory,
- wherein, if at least one core is determined to be a defective core:
- the non-volatile memory is operative to store information representing the defective data processing cores;
- and
- at least some of the plurality of data processing cores are capable of being removed from the interconnection system as function of the information representing the defective data processing cores.
8 more elements
An Integrated Circuit Data Processor, comprising:
- data processing cores arranged in an array;
- a plurality of the data processing cores comprise at least one Arithmetic Logic Unit;
- and
- at least some of the data processing cores operative to process different instructions at a single time;
- an interconnection system to which the plurality of data processing cores are connected;
- and
- a non-volatile memory, wherein, if at least one data processing cores is determined to be a defective core:
- the non-volatile memory is operative to store information representing the defective data processing cores;
- at least some of the plurality of data processing cores are removed from the interconnection system as function of the information representing the defective data processing cores.
6 more elements
An Integrated Circuit Data Processor, comprising:
- data processing cores arranged in an array;
- a plurality of the data processing cores comprise at least one Arithmetic Logic Unit;
- and
- at least some of the data processing cores being operative to process different instructions at a single time;
- an interconnection system to which the plurality of data processing cores are connected;
- and
- a non-volatile memory wherein, if at least one core is determined to be a defective core:
- the non-volatile memory is operative to store information representing the defective data processing cores;
- and
- at least some of the plurality of data processing cores are capable of being disconnected from the interconnection system as function of the information representing the defective data processing cores.
7 more elements
An Integrated Circuit Data Processor, comprising:
- data processing cores arranged in an array;
- a plurality of the data processing cores comprise at least one Arithmetic Logic Unit;
- and
- at least some of the data processing cores operative to process different instructions at a single time;
- an interconnection system to which the plurality of data processing cores are connected;
- and
- a non-volatile memory wherein, if at least one core is determined to be a defective core:
- the non-volatile memory is operative to store information representing the defective data processing cores;
- at least some of the plurality of data processing cores are disconnected from the interconnection system as function of the information representing the defective data processing cores.
6 more elements
An Integrated Circuit Data Processor comprising:
- a bus system;
- a plurality of data processing cores;
- each of the plurality of data processing cores comprises at least one Arithmetic and Logic unit;
- wherein the plurality of data processing cores are arranged in an arrangement having columns, the number of columns being larger than two, and
- the number of data processing cores in each column being larger than two;
- the bus system interconnects the plurality of data processing cores in the arrangement for transferring data between the data processing cores;
- and
- wherein, in view of a probability of the chip having defects already when being manufactured, more of the plurality of data processing cores are implemented than used, so that some of the data processing cores can be exempted from data transfer via the bus system in response to a chip test.
5 more elements
A Computer comprising:
- an Integrated Circuit Data Processor;
- and
- a storage media for storing at least one program for execution on the Integrated Circuit Data Processor;
- the Integrated Circuit Data Processor comprising
- a bus system;
- a plurality of data processing cores;
- each of the plurality of data processing cores comprises at least one Arithmetic and Logic unit;
- wherein the plurality of data processing cores are arranged in an arrangement having columns, the number of columns being larger than two, and
- the number of data processing cores in each column being larger than two;
- the bus system interconnects the plurality of data processing cores in the arrangement for transferring data between the data processing cores;
- and
- wherein, in view of a probability of the chip having defects already when being manufactured, more of the plurality of data processing cores are implemented than used, so that some of the data processing cores can be exempted from data transfer via the bus system in response to a chip test.
9 more elements
Dependencies are inferred from the claim text.