Apparatus and method for determining an operating condition of a memory cell based on cycle information
AssigneeSTEC, Inc.
InventorAshot Melik-Martirosian
Life of this patent
Estimating the term…
Abstract
Disclosed is an apparatus and method for adjusting a memory parameter in a non-volatile memory circuit. On a trigger event, a parameter is determined in accordance with a circuit characteristic associated with the memory block. The parameter may be a new read level voltage to apply to a page of a memory block, or a program verify level voltage used to program a page of a memory block. On determining the parameter a command is sent to the memory circuit to apply the parameter to the page of the memory block. The method can be triggered by an event such as P/E cycle times and the condition is dynamically adjusted to extend the life of the memory circuit.
Claims18
A method for adjusting memory parameters associated with a non-volatile memory circuit, comprising:
- monitoring a group of memory cells of the memory circuit for a trigger event, the trigger event occurring when a number of P/E cycles associated with the group of memory cells satisfies a cycle limit;
- and
- on the trigger event:
- determining an adjusted read level in accordance with a the number of P/E cycles associated with the group of memory cells based on indexing a lookup table by the number of P/E cycles to obtain the adjusted read level;
- and
- providing to the memory circuit a command to apply the determined adjusted read level to the group of memory cells of the memory circuit;
- wherein the adjusted read level is applied to subsequent read operations.
A system for adjusting memory parameters associated with a non-volatile memory circuit, comprising:
- a host interface configured to be operably coupled to a host device, to receive data from the host device, and to send data to the host device;
- a memory interface operably coupled to the memory circuit;
- and
- a controller operably coupled to the host interface, wherein the controller is operable to:
- monitor the memory circuit for a trigger event, the trigger event occurring when a number of P/E cycles associated with the group of memory cells satisfies a cycle limit;
- and
- on the trigger event:
- determine an adjusted read level in accordance with the number of P/E cycles associated with the group of memory cells based on indexing a lookup table by the number of P/E cycles to obtain the adjusted read level;
- and
- provide to the memory circuit a command to apply the determined adjusted read level to the group of memory cells of the memory circuit;
- wherein the adjusted read level is applied to subsequent read operations.
A method for adjusting memory parameters associated with a non-volatile memory circuit comprising:
- monitoring the memory circuit for a trigger event, the trigger event occurring when a retention time associated with a memory block of the memory circuit satisfies a retention limit;
- and
- on the trigger event:
- determining an adjusted program verify level in accordance with the retention time associated with the memory block by indexing a lookup table by the retention time to obtain the adjusted program verify level;
- and
- providing to the memory circuit a command to apply the determined adjusted program verify level to memory cells of the memory block.
A method for adjusting memory parameters associated with a non-volatile memory circuit comprising:
- monitoring the memory circuit for a trigger event, the trigger event occurring when a retention time associated with a memory block of the memory circuit satisfies a retention limit;
- and
- on the trigger event:
- determining an adjusted read level in accordance with the retention time associated with the memory block by indexing a lookup table by the retention time to obtain the adjusted read level;
- and
- providing to the memory circuit a command to apply the determined adjusted read level to memory cells of the memory block;
- wherein the adjusted read level is applied to subsequent read operations.
A system for adjusting memory parameters associated with a non-volatile memory circuit, comprising:
- a host interface configured to be operably coupled to a host device, to receive data from the host device, and to send data to the host device;
- a memory interface operably coupled to the memory circuit;
- and
- a controller operably coupled to the host interface, wherein the controller is operable to:
- monitor the memory circuit for a trigger event, the trigger event occurring when a retention time associated with a memory block of the memory circuit satisfies a retention limit;
- and
- on the trigger event:
- determine an adjusted program verify level in accordance with the retention time by indexing a lookup table by the retention time to obtain the adjusted program verify level;
- and
- provide to the memory circuit a command to apply the determined adjusted program verify level to memory cells of the memory block.
A system for adjusting memory parameters associated with a non-volatile memory circuit, comprising:
- a host interface configured to be operably coupled to a host device, to receive data from the host device, and to send data to the host device;
- a memory interface operably coupled to the memory circuit;
- and
- a controller operably coupled to the host interface, wherein the controller is operable to:
- monitor the memory circuit for a trigger event, the trigger event occurring when a retention time associated with a memory block of the memory circuit satisfies a retention limit;
- and
- on the trigger event:
- determine an adjusted read level in accordance with the retention time by indexing a lookup table by the retention time to obtain the adjusted read level;
- and
- provide to the memory circuit a command to apply the determined adjusted read level to memory cells of the memory block;
- wherein the adjusted read level is applied to subsequent read operations.
Dependencies are inferred from the claim text.