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US 8,819,485 B2Granted
Method and system for fault containment
AssigneeInfineon Technologies AG
InventorsAntonio Vilela, Andre Roger
Life of this patent
Estimating the term…
Abstract
Embodiments relate to systems and methods for error containment in a system comprising detecting an error by processing an input signal by multiple processing units, and delaying at least one output signal of a processing unit to enable, in case an error has been detected, modifying at least one output signal of the processing unit that would cause propagation of the error through the system.
Claims26
A system for avoiding error propagation in a multi-central processing unit (CPU) system comprising:
- a first CPU and at least one second CPU, the at least one second CPU adapted to operate in delayed lockstep configuration with the first CPU, wherein the first CPU and the at least one second CPU operate with a comparator to detect an error by comparing an output signal delayed by a delay unit from the first CPU with an output signal from the at least one second CPU not delayed by a delay unit;
- and
- an error blocking unit coupled to the comparator and the delay unit, wherein the output signal delayed by the delay unit from the first CPU is fed to the comparator and to the error blocking unit, and wherein the error blocking unit is configured
- to modify the output signal delayed by the delay unit from the first CPU when the comparator detects the error, such that the detected error is kept from propagating through the system.
1 more element
A system comprising:
- a first CPU coupled to receive an input signal;
- a second CPU;
- a first delay unit coupled to feed the input signal to the second CPU;
- a second delay unit coupled to delay an output signal of the first CPU related to write transactions of the first CPU;
- a first comparator unit coupled to compare at least one output signal of the first CPU via the second delay unit with at least one output signal of the second CPU, wherein the comparator unit is configured to:
- determine if an error occurred during processing the input signal by the first CPU or the second CPU, and
- output a corresponding error signal based on determination of an error;
- and
- a protected error blocking unit configured to receive and use the error signal to modify, under a protection condition, a write transaction of the first CPU such that the error is kept from propagating through the system.
6 more elements
A system comprising:
- a processing unit and at least one further processing unit, the latter configured to process an input signal with a predetermined delay with respect to the processing unit, and a comparator, collectively operable to detect a processing error by comparison of predetermined output signals of the processing unit and the at least one further processing unit;
- at least one delay unit adapted to delay at least one output signal of the processing unit to avoid unmodified propagation of at least one output signal of the processing unit through the system if a processing error has been detected by the comparator;
- and
- a protected error blocking unit configured to receive and use the result of said comparison of the predetermined output signals of the processing unit and the at least one further processing unit from the comparator to modify, under a protection condition, a write transaction of the processing unit such that the processing error is kept from propagating through the system.
1 more element
A method for avoiding error propagation in a multi-CPU system with a first CPU and at least a second CPU, the method comprising:
- operating at least one second CPU in delayed lockstep configuration with the first CPU;
- comparing at least one output signal of the first CPU with an at least one output signal of the at least one second CPU by a comparator, to detect an error in a form of at least one different processing result;
- and
- delaying at least one output signal of the first CPU related to a write transaction of the first CPU to modify at least one write transaction of the first CPU by an error blocking unit when the comparator detects the error, such that the detected error is kept from propagating through the system.
1 more element
A method for error containment in a system comprising:
- processing an input signal by a processing unit and at least one further processing unit;
- comparing the processing results of the processing unit and the at least one further processing unit to detect an error in a form of at least one different processing result;
- and
- delaying at least one output signal of the processing unit to enable, in case an error has been detected, modifying at least one output signal of the processing unit by an error block unit, that would otherwise cause propagation of the error through the system.
1 more element
A method for error containment in a system comprising:
- detecting an error by processing an input signal by multiple processing units and comparing processing results;
- and
- delaying at least one output signal of a processing unit to enable, in case an error has been detected, modifying at least one output signal of the processing unit by an error blocking unit, that would otherwise cause propagation of the error through the system.
Dependencies are inferred from the claim text.