Memory access circuit and memory access system

A memory access system comprising:

• a memory comprising a parallel interface;
• a system circuit configured to issue a memory access command to command an access to the memory;
• and
• a memory access circuit connected to the memory and the system circuit;
• wherein
• the memory access circuit comprises,
• a phase locked loop configured to generate a PLL (Phase Locked Loop) output locked to a reference frequency of a reference signal,
• a first phy-clock tree configured to delay the PLL output and to generate a reference clock signal,
• a first delay locked loop configured to correct a clock skew between the reference clock signal and a system clock signal generated by the system circuit, and to generate a source signal of the system clock signal,
• a second delay locked loop configured to correct a clock skew between the reference clock signal and a phy-clock signal used in the memory access circuit, and to generate a source signal of the phy-clock signal,
• a first phase detector configured to detect a phase difference between the system clock signal and the phy-clock signal, and to generate a first detection signal corresponding to the phase difference,
• a second phase detector configured to detect a phase difference between the system clock signal and the phy-clock signal, and to generate a second detection signal corresponding to the phase difference;
• and
• a master delay locked loop configured to count the reference clock signal and to generate a delay correction signal, wherein
• the first delay locked loop determines a correction direction and a correction amount based on the first detection signal and the delay correction signal, respectively;
• and
• the second delay locked loop determines a correction direction and a correction amount based on the second detection signal and the delay correction signal, respectively.

A memory access circuit connected to a memory comprising a parallel interface and a system circuit configured to issue a memory access command to command access to the memory and to generate a system clock signal;

• the memory access circuit comprising:
• a phase locked loop configured to generate a PLL (Phase Locked Loop) output locked to a reference frequency of a reference signal from the system clock signal;
• a first phy-clock tree configured to delay the PLL output and to generate a reference clock signal;
• a delay locked loop configured to correct a clock skew between the reference clock signal and a phy clock signal used in the memory access circuit and to generate a source signal of the phy-clock signal;
• a phase detector configured to detect a phase difference between the reference clock signal and the phy-clock signal, and to generate a detection signal corresponding to the phase difference;
• and
• a master delay locked loop configured to count the reference clock signal and to generate a delay correction signal, wherein
• the delay locked loop determines a correction direction and a correction amount based on the detection signal and the delay correction signal, respectively.