Active training of memory command timing

A method comprising:

• setting a CMD delay setting for a CMD/CTL interconnect linking a memory controller with a memory subsystem;
• setting a CTL delay setting for the CMD/CTL interconnect linking the memory controller with the memory subsystem;
• setting an initial CLK delay setting according to one of the following operations:
• (i) statically programming a delay setting for each of the CMD delay setting and the CTL delay setting and then moving the initial CLK delay setting with respect to the CMD delay setting and the CTL delay setting to determine which of a plurality of alignments are valid,
• (ii) statically programming the CTL delay setting versus the initial CLK delay setting and then moving the initial CLK delay setting and the CTL delay setting together to determine which of the plurality of alignments are valid, and
• (iii) using a two stage training flow in which the operation at (i) and then the operation at (ii) are each performed in successive stages;
• iterating through a plurality of CLK delay settings to an interconnect training mechanism located in the memory controller;
• for each of the plurality of CLK delay settings, recording a pass or a fail result provided by the interconnect training mechanism, wherein a programmable width step size is pre-selected to step between each iteration to produce a desirable tradeoff between accuracy and runtime, in which the programmable width step size avoids iterating through all possible iterations for the CLK delay setting;
• finding, via the interconnect training mechanism, the largest range of CLK delay settings that produced a passing result and selects the largest range of CLK delay settings that produced the passing result;
• and
• selecting one of the plurality of CLK delay settings based, at least in part, on the results of iterating through the plurality of CLK delay settings provided by the interconnect training mechanism and setting a CLK delay to a center of the selected largest range of the CLK delay settings that produced the passing result.

A system comprising:

• a memory controller including an interconnect training mechanism;
• and
• an integrated circuit coupled with the memory controller, the integrated circuit including,
• logic to set a CMD delay setting and to set a CTL delay setting for a CMD/CTL interconnect linking a memory controller with a dynamic random access memory (DRAM) memory subsystem,
• logic to set an initial CLK delay setting according to one of the following operations:
• (i) statically programming a delay setting for each of the CMD delay setting and the CTL delay setting and then moving the initial CLK delay setting with respect to the CMD delay setting and the CTL delay setting to determine which of a plurality of alignments are valid,
• (ii) statically programming the CTL delay setting versus the initial CLK delay setting and then moving the initial CLK delay setting and the CTL delay setting together to determine which of the plurality of alignments are valid, and
• (iii) using a two stage training flow in which the operation at (i) and then the operation at (ii) are each performed in successive stages,
• logic to iterate through a plurality of CLK delay settings to an interconnect training mechanism located in the memory controller and, for each of the plurality of CLK delay settings,
• logic to record a pass or a fail result provided by the interconnect training mechanism, wherein a programmable width step size is pre-selected to step between each iteration to produce a desirable tradeoff between accuracy and runtime, in which the programmable width step size avoids iterating through all possible iterations for the CLK delay setting;
• logic to select one of the plurality of CLK delay settings based, at least in part, on the results of the logic to iterate through the plurality of CLK delay settings provided by the interconnect training, wherein the interconnect training mechanism finds the largest range of CLK delay settings that produced a passing result and selects the largest range of CLK delay settings that produced the passing result, and
• logic to set a CLK delay to the selected largest range of CLK delay settings that produced the passing result by setting the CLK delay to a center of the selected largest range.