Method and system for clock edge synchronization of multiple clock distribution integrated circuits by configuring master device to produce at least one gated clock output signal

An apparatus for clock edge synchronization among a plurality of devices, comprising:

• a master device configured for providing at least one gated master output clock signal for driving one or more slave devices and one or more other gated master output clock signals based on a synchronization input signal and an input clock signal;
• one or more slave devices configured for producing one or more slave output clock signals based on the synchronization input signal and at least one gated master output clock signal, wherein
• the one or more slave output clock signals are clock edge synchronized, and
• the one or more other gated master output clock signals are clock edge synchronized with the slave output clock signals.

An apparatus for clock edge synchronization among a plurality of devices, comprising:

• a master device configured for providing one or more gated master output clock signals based on a synchronization input signal and an input clock signal;
• one or more slave devices configured for producing one or more slave output clock signals based on the synchronization input signal and at least one gated master output clock signal, wherein
• the master device comprises one or more clock distribution circuits, each of which generates a corresponding gated master output clock signal, and wherein
• each gated master output clock signal is configurable selectively for driving a slave device or for being a master output clock signal that is clock edge synchronized with the slave output clock signals.

A master device apparatus for clock edge synchronization among a plurality of devices, comprising:

• a master device configured for providing one or more gated master output clock signals based on a synchronization input signal and an input clock signal;
• wherein the master device comprises:
• a synchronization signal delay circuit configured for receiving a synchronization input signal and delaying the synchronization input signal for a first defined period to produce a delayed synchronization signal;
• a first re-timing circuit configured for re-timing, with respect to a master clock input signal, the delayed synchronization signal being provided to generate a first master internal synchronization signal;
• and
• one or more clock distribution circuits configured to each produce one or more gated master clock output signals based on the master clock input signal and the first master internal synchronization signal;
• and wherein
• the one or more clock distribution circuits each is configured to drive one or more slave devices, having slave output clock signals, at one or more frequencies and are clock edge synchronized with all slave output clock signals.