US 8,819,461 B2 · Method, apparatus, and system for energy efficiency and energy conservation including improved processor core deep power down exit latency by using register secondary uninterrupted power supply

Abstract

Embodiments of the invention relate to improving exit latency from computing device processor core deep power down. Processor state data may be maintained during deep power down mode by providing a secondary uninterrupted voltage supply to always on keeper circuits that reside within critical state registers of the processor. When these registers receive a control signal indicating that the processor power state is going to be reduced from an active processor power state to a zero processor power state, they write critical state data from the critical state register latches to the keeper circuits that are supplied with the uninterrupted power. Then, when a register receives a control signal indicating that a processor power state of the processor is going to be increased back to an active processor power state, the critical state data stored in the keeper circuits is written back to the critical state register latches.

Claims20

Dependent claims

A method comprising:

signaling at least one of a plurality of state registers of a processor that a processor power state of the processor is going to be changed to a zero processor power state from an active processor power state;
based on the signaling, writing data stored as a plurality of state bits of the at least one of plurality of state registers to always on circuitry in the at least one register of the plurality of registers;
changing a processor power state of the processor and of the state bits from the active processor power state to the zero processor power state to reduce power consumption, while maintaining a processor power state of the always on circuitry to maintain the plurality of state data stored in the always on circuitry.

An apparatus comprising:

a processor die comprising a power control unit coupled to an execution unit, the execution unit having a state register having a storage for a number state bits during an active processor power state and separate always on circuitry to store corresponding state data from the state bits during a zero processor power state;
the power control unit configured to signal the state register that a processor power state of the processor is going to be changed from the active processor power state to a zero processor power state;
the state register configured to, based on the signal, write a plurality of state data stored in the plurality of state bits to the corresponding always on circuitry;
the power control unit configured to signal a first power supply of the processor to change a processor power state of the processor and of the state bits from the active processor power state to the zero processor power state;
the power control unit configured to maintain power of a second power supply unit of the processor, during the zero processor power state, to maintain a processor power state of the always on circuitry to maintain the plurality of state data stored in the always on circuitry.

2 more elements

A system comprising:

memory to store a program;
a processor die coupled to the memory to process data stored in the memory;
a processor die comprising a power control unit coupled to an execution unit, the execution unit having a state register having a storage for a number state bits during an active processor power state and separate always on circuitry to store corresponding state data from the state bits during a zero processor power state;
the power control unit configured to signal the state register that a processor power state of the processor is going to be changed from an active processor power state to a zero processor power state;
the state register configured to, based on the signal, write a plurality of state data stored in the plurality of state bits to the corresponding always on circuitry;
the power control unit configured to signal a first power supply of the processor to change a processor power state of the processor and of the state bits from the active processor power state to the zero processor power state;
the power control unit configured to maintain power of a second power supply unit of the processor, during the zero processor power state, to maintain a processor power state of the always on circuitry to maintain the plurality of state data stored in the always on circuitry.

4 more elements

Dependencies are inferred from the claim text.

Method, apparatus, and system for energy efficiency and energy conservation including improved processor core deep power down exit latency by using register secondary uninterrupted power supply

Life of this patent

Method, apparatus, and system for energy efficiency and energy conservation including improved processor core deep power down exit latency by using register secondary uninterrupted power supply

Life of this patent

Abstract

Claims20