Variable length stages in a pipeline

A method to vary a length of a plurality of stages in a pipeline, comprising the steps of:

• (A) operating said pipeline in a first mode such that said stages are linked in series by a plurality of registers, said registers being governed by a clock signal having a first frequency in said first mode;
• (B) operating said pipeline in a second mode in which said clock signal has a second frequency;
• (C) bypassing a first particular one of said registers while in said second mode to form a first combined stage, said first combined stage comprising a first of said stages adjoining said first particular register and a second of said stages adjoining said first particular register;
• and
• (D) operating said pipeline in a third mode in response to an assertion of a control signal, wherein (i) said third mode transitions said pipeline from said first mode to said second mode, (ii) said clock signal is halted during all of said third mode, (iii) said third mode is at least as long as a period of said second frequency and (iv) said pipeline is filled with a plurality of non-operation commands by an end of said first mode in preparation to enter said third mode.

A processor comprising:

• means for (i) operating a pipeline in a first mode such that a plurality of stages in said pipeline are linked in series by a plurality of registers, said registers being governed by a clock signal having a first frequency in said first mode and (ii) operating said pipeline in a second mode in which said clock signal has a second frequency;
• means for bypassing a first particular one of said registers while in said second mode to form a first combined stage, said first combined stage comprising a first of said stages adjoining said first particular register and a second of said stages adjoining said first particular register;
• and
• means for operating said pipeline in a third mode in response to an assertion of a control signal, wherein (i) said third mode transitions said pipeline from said first mode to said second mode, (ii) said clock signal is halted during all of said third mode, (iii) said third mode is at least as long as a period of said second frequency and (iv) said pipeline is filled with a plurality of non-operation commands by an end of said first mode in preparation to enter said third mode.